Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	917642	1			T3	42		T4	2327		T43	1260
auto[1]	10288751	1			T3	358		T4	7381		T13	2361
auto[2]	702815	1			T3	27		T4	1701		T43	1160
auto[3]	10009266	1			T3	204		T4	6772		T13	2266

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14338130	1			T3	475		T4	263		T13	3014
auto[1]	2012286	1			T3	64		T4	1806		T13	729
auto[2]	2044803	1			T3	84		T4	2492		T13	728
auto[3]	3523255	1			T3	8		T4	13620		T13	156

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8857239

1

T3

631

T4

9

T13

4627

auto[1]

13061235

1

T4

18172

T32

1

T20

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	302014	1			T3	35		T43	1052		T44	4
auto[0]	auto[0]	auto[1]	31416	1			T3	3		T43	96		T44	6
auto[0]	auto[0]	auto[2]	31651	1			T3	4		T43	102		T44	7
auto[0]	auto[0]	auto[3]	69521	1			T4	3		T43	10		T44	41
auto[0]	auto[1]	auto[0]	3241637	1			T3	286		T13	1530		T32	27039
auto[0]	auto[1]	auto[1]	336691	1			T3	44		T13	377		T32	2522
auto[0]	auto[1]	auto[2]	337750	1			T3	26		T13	376		T32	2745
auto[0]	auto[1]	auto[3]	234450	1			T3	2		T4	2		T13	78
auto[0]	auto[2]	auto[0]	210257	1			T43	994		T44	4		T72	12
auto[0]	auto[2]	auto[1]	26393	1			T43	82		T44	4		T85	4
auto[0]	auto[2]	auto[2]	27421	1			T3	23		T43	72		T44	4
auto[0]	auto[2]	auto[3]	49369	1			T3	4		T4	1		T43	12
auto[0]	auto[3]	auto[0]	3091607	1			T3	154		T13	1484		T32	27103
auto[0]	auto[3]	auto[1]	320615	1			T3	17		T13	352		T32	2735
auto[0]	auto[3]	auto[2]	339120	1			T3	31		T13	352		T32	2429
auto[0]	auto[3]	auto[3]	207327	1			T3	2		T4	3		T13	78
auto[1]	auto[0]	auto[0]	15908	1			T4	66		T105	112		T106	78
auto[1]	auto[0]	auto[1]	71719	1			T4	357		T105	438		T106	350
auto[1]	auto[0]	auto[2]	71376	1			T4	351		T105	439		T106	358
auto[1]	auto[0]	auto[3]	324037	1			T4	1550		T105	2040		T106	1726
auto[1]	auto[1]	auto[0]	3733623	1			T4	131		T32	1		T20	2
auto[1]	auto[1]	auto[1]	609768	1			T4	1172		T103	5168		T104	6036
auto[1]	auto[1]	auto[2]	580617	1			T4	657		T20	1		T103	5794
auto[1]	auto[1]	auto[3]	1214215	1			T4	5419		T45	1		T103	468
auto[1]	auto[2]	auto[0]	11873	1			T138	938		T139	403		T140	693
auto[1]	auto[2]	auto[1]	53707	1			T138	4469		T139	1643		T140	3081
auto[1]	auto[2]	auto[2]	58718	1			T4	298		T105	413		T106	339
auto[1]	auto[2]	auto[3]	265077	1			T4	1402		T105	1742		T106	1533
auto[1]	auto[3]	auto[0]	3731211	1			T4	66		T45	2		T103	58757
auto[1]	auto[3]	auto[1]	561977	1			T4	277		T103	5672		T104	6120
auto[1]	auto[3]	auto[2]	598150	1			T4	1186		T103	5126		T104	6090
auto[1]	auto[3]	auto[3]	1159259	1			T4	5240		T103	474		T104	568