Module Definition
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Module : prim_generic_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_ram_1p_scr.u_read_en_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_ram_1p_scr.u_write_en_d_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_ram_1p_scr.u_addr_match_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_ram_1p_scr.u_intg_error.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_req_d_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_write_d_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_seed_anchor.u_secure_anchor_buf.gen_generic.u_impl_generic


Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_ram_1p_scr.u_read_en_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_en_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_ram_1p_scr.u_write_en_d_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_write_en_d_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_ram_1p_scr.u_addr_match_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_addr_match_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_ram_1p_scr.u_intg_error.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_intg_error


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_req_d_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_req_d_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_write_d_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_write_d_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[4].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[5].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[6].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[7].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_buf
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.u_read_en_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.u_write_en_d_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.u_addr_match_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.u_intg_error.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_req_d_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_write_d_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%