Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1097161421	201665	0	0
ctrl_regwen_rd_A	1097161421	4369	0	0
exec_rd_A	1097161421	4231	0	0
exec_regwen_rd_A	1097161421	4468	0	0
readback_rd_A	1097161421	3134	0	0
readback_regwen_rd_A	1097161421	2826	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097161421	201665	0	0
T2	110099	6774	0	0
T3	642165	0	0	0
T4	935280	0	0	0
T5	138165	0	0	0
T9	34327	0	0	0
T10	263001	0	0	0
T11	1126	0	0	0
T12	197188	0	0	0
T13	72671	0	0	0
T27	0	1061	0	0
T28	898744	0	0	0
T29	0	4415	0	0
T38	0	3125	0	0
T51	0	6716	0	0
T61	0	4744	0	0
T62	0	5675	0	0
T73	0	4787	0	0
T74	0	3743	0	0
T75	0	3174	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097161421	4369	0	0
T23	156577	0	0	0
T30	261605	0	0	0
T38	69583	260	0	0
T39	72041	0	0	0
T40	207304	0	0	0
T41	317942	0	0	0
T42	157940	0	0	0
T49	0	229	0	0
T51	0	250	0	0
T58	262953	0	0	0
T109	0	156	0	0
T110	0	33	0	0
T111	0	497	0	0
T112	0	87	0	0
T113	0	201	0	0
T114	0	200	0	0
T115	0	311	0	0
T116	85404	0	0	0
T117	33463	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097161421	4231	0	0
T23	156577	0	0	0
T30	261605	0	0	0
T38	69583	301	0	0
T39	72041	0	0	0
T40	207304	0	0	0
T41	317942	0	0	0
T42	157940	0	0	0
T49	0	273	0	0
T51	0	284	0	0
T58	262953	0	0	0
T109	0	183	0	0
T110	0	16	0	0
T111	0	368	0	0
T112	0	78	0	0
T113	0	236	0	0
T114	0	218	0	0
T115	0	360	0	0
T116	85404	0	0	0
T117	33463	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097161421	4468	0	0
T23	156577	0	0	0
T30	261605	0	0	0
T38	69583	276	0	0
T39	72041	0	0	0
T40	207304	0	0	0
T41	317942	0	0	0
T42	157940	0	0	0
T49	0	280	0	0
T51	0	265	0	0
T58	262953	0	0	0
T109	0	170	0	0
T110	0	17	0	0
T111	0	467	0	0
T112	0	141	0	0
T113	0	231	0	0
T114	0	198	0	0
T115	0	279	0	0
T116	85404	0	0	0
T117	33463	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097161421	3134	0	0
T23	156577	0	0	0
T30	261605	0	0	0
T38	69583	270	0	0
T39	72041	0	0	0
T40	207304	0	0	0
T41	317942	0	0	0
T42	157940	0	0	0
T49	0	164	0	0
T51	0	256	0	0
T58	262953	0	0	0
T109	0	219	0	0
T110	0	7	0	0
T111	0	413	0	0
T112	0	152	0	0
T113	0	215	0	0
T114	0	175	0	0
T115	0	241	0	0
T116	85404	0	0	0
T117	33463	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1097161421	2826	0	0
T23	156577	0	0	0
T30	261605	0	0	0
T38	69583	241	0	0
T39	72041	0	0	0
T40	207304	0	0	0
T41	317942	0	0	0
T42	157940	0	0	0
T49	0	185	0	0
T51	0	198	0	0
T58	262953	0	0	0
T109	0	147	0	0
T110	0	1	0	0
T111	0	322	0	0
T112	0	122	0	0
T113	0	244	0	0
T114	0	171	0	0
T115	0	208	0	0
T116	85404	0	0	0
T117	33463	0	0	0