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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1033
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T789 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1008811286 Aug 09 06:41:13 PM PDT 24 Aug 09 06:42:03 PM PDT 24 7352109900 ps
T790 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1787074421 Aug 09 06:47:25 PM PDT 24 Aug 09 07:07:26 PM PDT 24 25257701247 ps
T791 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1671646143 Aug 09 06:42:54 PM PDT 24 Aug 09 06:43:35 PM PDT 24 6278557179 ps
T792 /workspace/coverage/default/20.sram_ctrl_executable.3132907217 Aug 09 06:43:09 PM PDT 24 Aug 09 06:50:05 PM PDT 24 9426594322 ps
T793 /workspace/coverage/default/43.sram_ctrl_max_throughput.3291129367 Aug 09 06:49:48 PM PDT 24 Aug 09 06:50:32 PM PDT 24 1696789597 ps
T794 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1855491036 Aug 09 06:42:02 PM PDT 24 Aug 09 07:10:05 PM PDT 24 61155065514 ps
T795 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1913342522 Aug 09 06:46:30 PM PDT 24 Aug 09 06:53:18 PM PDT 24 76946852882 ps
T796 /workspace/coverage/default/10.sram_ctrl_multiple_keys.2289342835 Aug 09 06:41:38 PM PDT 24 Aug 09 07:09:24 PM PDT 24 41687390227 ps
T797 /workspace/coverage/default/8.sram_ctrl_regwen.614938028 Aug 09 06:41:37 PM PDT 24 Aug 09 06:51:07 PM PDT 24 17665447926 ps
T798 /workspace/coverage/default/13.sram_ctrl_alert_test.231056901 Aug 09 06:41:58 PM PDT 24 Aug 09 06:41:58 PM PDT 24 39332563 ps
T799 /workspace/coverage/default/13.sram_ctrl_multiple_keys.4004716976 Aug 09 06:41:47 PM PDT 24 Aug 09 06:53:08 PM PDT 24 61085143540 ps
T800 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.4265161916 Aug 09 06:45:34 PM PDT 24 Aug 09 06:52:13 PM PDT 24 17612320796 ps
T801 /workspace/coverage/default/7.sram_ctrl_alert_test.35415003 Aug 09 06:41:31 PM PDT 24 Aug 09 06:41:32 PM PDT 24 198741123 ps
T802 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.526430750 Aug 09 06:43:19 PM PDT 24 Aug 09 06:49:04 PM PDT 24 23557842579 ps
T803 /workspace/coverage/default/36.sram_ctrl_alert_test.1832995616 Aug 09 06:47:16 PM PDT 24 Aug 09 06:47:17 PM PDT 24 14969872 ps
T804 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4088244956 Aug 09 06:42:09 PM PDT 24 Aug 09 06:44:58 PM PDT 24 18244217419 ps
T805 /workspace/coverage/default/27.sram_ctrl_mem_walk.1970252123 Aug 09 06:44:45 PM PDT 24 Aug 09 06:47:48 PM PDT 24 10787050607 ps
T806 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3836955402 Aug 09 06:43:03 PM PDT 24 Aug 09 06:47:12 PM PDT 24 8291953311 ps
T807 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2287350776 Aug 09 06:44:46 PM PDT 24 Aug 09 06:51:14 PM PDT 24 5450372612 ps
T808 /workspace/coverage/default/19.sram_ctrl_ram_cfg.3133620851 Aug 09 06:42:54 PM PDT 24 Aug 09 06:42:57 PM PDT 24 364716476 ps
T809 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3683834444 Aug 09 06:41:47 PM PDT 24 Aug 09 06:43:32 PM PDT 24 794592270 ps
T810 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2978328341 Aug 09 06:41:05 PM PDT 24 Aug 09 06:47:47 PM PDT 24 5234893712 ps
T811 /workspace/coverage/default/12.sram_ctrl_regwen.1496739461 Aug 09 06:41:50 PM PDT 24 Aug 09 07:02:22 PM PDT 24 20555537728 ps
T812 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1342593333 Aug 09 06:45:40 PM PDT 24 Aug 09 06:45:43 PM PDT 24 356034103 ps
T813 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2258955006 Aug 09 06:51:09 PM PDT 24 Aug 09 07:24:14 PM PDT 24 67997895182 ps
T814 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.387766713 Aug 09 06:46:14 PM PDT 24 Aug 09 06:51:04 PM PDT 24 7050158440 ps
T815 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2238640306 Aug 09 06:43:43 PM PDT 24 Aug 09 06:49:06 PM PDT 24 13847775234 ps
T816 /workspace/coverage/default/43.sram_ctrl_smoke.890237689 Aug 09 06:49:27 PM PDT 24 Aug 09 06:49:36 PM PDT 24 1275392381 ps
T817 /workspace/coverage/default/26.sram_ctrl_alert_test.3724939196 Aug 09 06:44:29 PM PDT 24 Aug 09 06:44:30 PM PDT 24 20055693 ps
T818 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.4028841072 Aug 09 06:47:31 PM PDT 24 Aug 09 06:48:58 PM PDT 24 36762022778 ps
T819 /workspace/coverage/default/19.sram_ctrl_smoke.1503714745 Aug 09 06:42:48 PM PDT 24 Aug 09 06:43:00 PM PDT 24 5352752788 ps
T820 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2621814572 Aug 09 06:42:05 PM PDT 24 Aug 09 06:42:15 PM PDT 24 708684727 ps
T821 /workspace/coverage/default/1.sram_ctrl_stress_all.952121152 Aug 09 06:41:11 PM PDT 24 Aug 09 07:51:35 PM PDT 24 1415494031039 ps
T822 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1731568386 Aug 09 06:44:29 PM PDT 24 Aug 09 06:45:00 PM PDT 24 3618629451 ps
T823 /workspace/coverage/default/17.sram_ctrl_bijection.659814506 Aug 09 06:42:31 PM PDT 24 Aug 09 06:52:35 PM PDT 24 91120925000 ps
T824 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.791030745 Aug 09 06:44:01 PM PDT 24 Aug 09 06:44:09 PM PDT 24 210182401 ps
T825 /workspace/coverage/default/32.sram_ctrl_alert_test.264852012 Aug 09 06:46:10 PM PDT 24 Aug 09 06:46:11 PM PDT 24 12130124 ps
T826 /workspace/coverage/default/7.sram_ctrl_ram_cfg.1813274440 Aug 09 06:41:29 PM PDT 24 Aug 09 06:41:32 PM PDT 24 373630169 ps
T827 /workspace/coverage/default/17.sram_ctrl_multiple_keys.3305494844 Aug 09 06:42:34 PM PDT 24 Aug 09 06:43:04 PM PDT 24 1851104458 ps
T828 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2510517207 Aug 09 06:43:36 PM PDT 24 Aug 09 06:46:17 PM PDT 24 8932510711 ps
T829 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3333339735 Aug 09 06:41:39 PM PDT 24 Aug 09 06:46:52 PM PDT 24 10523436636 ps
T830 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2207568774 Aug 09 06:41:35 PM PDT 24 Aug 09 06:42:34 PM PDT 24 8989913143 ps
T831 /workspace/coverage/default/31.sram_ctrl_partial_access.1300749993 Aug 09 06:45:35 PM PDT 24 Aug 09 06:46:02 PM PDT 24 12327724789 ps
T832 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3026505273 Aug 09 06:41:44 PM PDT 24 Aug 09 06:43:04 PM PDT 24 6162861216 ps
T833 /workspace/coverage/default/6.sram_ctrl_smoke.2112704542 Aug 09 06:41:30 PM PDT 24 Aug 09 06:41:37 PM PDT 24 387639757 ps
T834 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3687848030 Aug 09 06:51:08 PM PDT 24 Aug 09 06:51:23 PM PDT 24 446057244 ps
T835 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3997033996 Aug 09 06:49:26 PM PDT 24 Aug 09 06:52:23 PM PDT 24 10272751187 ps
T836 /workspace/coverage/default/6.sram_ctrl_executable.2732509712 Aug 09 06:41:28 PM PDT 24 Aug 09 07:00:33 PM PDT 24 124255276026 ps
T837 /workspace/coverage/default/38.sram_ctrl_executable.2248118312 Aug 09 06:47:58 PM PDT 24 Aug 09 07:03:52 PM PDT 24 69554054844 ps
T838 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2897538978 Aug 09 06:45:54 PM PDT 24 Aug 09 06:46:39 PM PDT 24 6818135594 ps
T839 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4000660946 Aug 09 06:41:32 PM PDT 24 Aug 09 06:42:48 PM PDT 24 2747718414 ps
T840 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2692081725 Aug 09 06:49:59 PM PDT 24 Aug 09 06:50:19 PM PDT 24 784809701 ps
T841 /workspace/coverage/default/18.sram_ctrl_stress_all.1515399387 Aug 09 06:42:48 PM PDT 24 Aug 09 07:33:44 PM PDT 24 92739557134 ps
T842 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1716411205 Aug 09 06:43:43 PM PDT 24 Aug 09 06:53:25 PM PDT 24 4864149840 ps
T843 /workspace/coverage/default/40.sram_ctrl_regwen.911917657 Aug 09 06:48:49 PM PDT 24 Aug 09 06:59:59 PM PDT 24 13839095862 ps
T844 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3665452505 Aug 09 06:41:38 PM PDT 24 Aug 09 06:55:11 PM PDT 24 13471852322 ps
T845 /workspace/coverage/default/41.sram_ctrl_executable.2735865168 Aug 09 06:48:57 PM PDT 24 Aug 09 06:59:03 PM PDT 24 13454773884 ps
T846 /workspace/coverage/default/36.sram_ctrl_smoke.3840997543 Aug 09 06:46:57 PM PDT 24 Aug 09 06:49:23 PM PDT 24 481757579 ps
T847 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3697237965 Aug 09 06:47:17 PM PDT 24 Aug 09 06:51:55 PM PDT 24 4557336884 ps
T848 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3965803502 Aug 09 06:48:59 PM PDT 24 Aug 09 06:51:24 PM PDT 24 9069128995 ps
T849 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3434263862 Aug 09 06:47:57 PM PDT 24 Aug 09 06:53:06 PM PDT 24 6328249712 ps
T850 /workspace/coverage/default/34.sram_ctrl_mem_walk.3893494916 Aug 09 06:46:36 PM PDT 24 Aug 09 06:48:46 PM PDT 24 7897930341 ps
T851 /workspace/coverage/default/37.sram_ctrl_mem_walk.4038918368 Aug 09 06:47:33 PM PDT 24 Aug 09 06:50:17 PM PDT 24 24754798305 ps
T852 /workspace/coverage/default/22.sram_ctrl_multiple_keys.4091483183 Aug 09 06:43:27 PM PDT 24 Aug 09 06:48:44 PM PDT 24 14266392472 ps
T853 /workspace/coverage/default/27.sram_ctrl_lc_escalation.3699861755 Aug 09 06:44:46 PM PDT 24 Aug 09 06:45:49 PM PDT 24 9141482411 ps
T854 /workspace/coverage/default/20.sram_ctrl_bijection.2228791772 Aug 09 06:43:04 PM PDT 24 Aug 09 07:28:06 PM PDT 24 137523035164 ps
T855 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1197763816 Aug 09 06:44:15 PM PDT 24 Aug 09 06:45:37 PM PDT 24 60194261327 ps
T856 /workspace/coverage/default/29.sram_ctrl_mem_walk.2140245178 Aug 09 06:45:13 PM PDT 24 Aug 09 06:49:31 PM PDT 24 13590595127 ps
T857 /workspace/coverage/default/3.sram_ctrl_multiple_keys.1507254425 Aug 09 06:41:15 PM PDT 24 Aug 09 06:45:58 PM PDT 24 16041993415 ps
T858 /workspace/coverage/default/8.sram_ctrl_max_throughput.1440421435 Aug 09 06:41:36 PM PDT 24 Aug 09 06:43:33 PM PDT 24 792614152 ps
T859 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2508762053 Aug 09 06:41:26 PM PDT 24 Aug 09 06:51:01 PM PDT 24 49116342266 ps
T860 /workspace/coverage/default/4.sram_ctrl_executable.1535552634 Aug 09 06:41:19 PM PDT 24 Aug 09 07:00:38 PM PDT 24 9512268109 ps
T861 /workspace/coverage/default/47.sram_ctrl_executable.2115399394 Aug 09 06:50:37 PM PDT 24 Aug 09 07:12:32 PM PDT 24 83839408258 ps
T862 /workspace/coverage/default/45.sram_ctrl_partial_access.2636274571 Aug 09 06:50:07 PM PDT 24 Aug 09 06:50:16 PM PDT 24 445322560 ps
T863 /workspace/coverage/default/14.sram_ctrl_alert_test.1625324875 Aug 09 06:42:10 PM PDT 24 Aug 09 06:42:10 PM PDT 24 57126839 ps
T864 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.581785576 Aug 09 06:51:08 PM PDT 24 Aug 09 06:51:44 PM PDT 24 1090062874 ps
T865 /workspace/coverage/default/25.sram_ctrl_regwen.178491908 Aug 09 06:44:15 PM PDT 24 Aug 09 06:55:38 PM PDT 24 25883111497 ps
T866 /workspace/coverage/default/21.sram_ctrl_lc_escalation.1144699092 Aug 09 06:43:19 PM PDT 24 Aug 09 06:43:42 PM PDT 24 4066638046 ps
T867 /workspace/coverage/default/36.sram_ctrl_multiple_keys.3849157045 Aug 09 06:46:56 PM PDT 24 Aug 09 07:08:43 PM PDT 24 41417634347 ps
T868 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3295309185 Aug 09 06:45:54 PM PDT 24 Aug 09 06:52:00 PM PDT 24 63106435147 ps
T869 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3523869252 Aug 09 06:51:10 PM PDT 24 Aug 09 06:52:32 PM PDT 24 13058392102 ps
T870 /workspace/coverage/default/19.sram_ctrl_stress_all.3896330525 Aug 09 06:43:04 PM PDT 24 Aug 09 08:55:08 PM PDT 24 49421985593 ps
T871 /workspace/coverage/default/15.sram_ctrl_multiple_keys.1689509142 Aug 09 06:42:09 PM PDT 24 Aug 09 06:59:10 PM PDT 24 6326748253 ps
T872 /workspace/coverage/default/42.sram_ctrl_ram_cfg.215755296 Aug 09 06:49:26 PM PDT 24 Aug 09 06:49:29 PM PDT 24 352676191 ps
T873 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1996091455 Aug 09 06:43:10 PM PDT 24 Aug 09 06:45:35 PM PDT 24 5047915245 ps
T874 /workspace/coverage/default/10.sram_ctrl_alert_test.836499783 Aug 09 06:41:49 PM PDT 24 Aug 09 06:41:50 PM PDT 24 16652816 ps
T875 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3358845354 Aug 09 06:41:05 PM PDT 24 Aug 09 06:42:16 PM PDT 24 3077999396 ps
T876 /workspace/coverage/default/9.sram_ctrl_mem_walk.4135625982 Aug 09 06:41:37 PM PDT 24 Aug 09 06:45:54 PM PDT 24 15161994938 ps
T877 /workspace/coverage/default/21.sram_ctrl_partial_access.803706554 Aug 09 06:43:18 PM PDT 24 Aug 09 06:43:27 PM PDT 24 389355411 ps
T878 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3211504985 Aug 09 06:51:09 PM PDT 24 Aug 09 06:52:05 PM PDT 24 38263833965 ps
T879 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1025369477 Aug 09 06:44:53 PM PDT 24 Aug 09 06:57:31 PM PDT 24 25338242596 ps
T880 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3535806992 Aug 09 06:41:13 PM PDT 24 Aug 09 06:44:38 PM PDT 24 7233373035 ps
T881 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1616629492 Aug 09 06:45:14 PM PDT 24 Aug 09 06:46:44 PM PDT 24 10713525632 ps
T882 /workspace/coverage/default/9.sram_ctrl_max_throughput.575601517 Aug 09 06:41:38 PM PDT 24 Aug 09 06:42:34 PM PDT 24 1468337080 ps
T883 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.995018584 Aug 09 06:47:25 PM PDT 24 Aug 09 06:47:37 PM PDT 24 3847465727 ps
T884 /workspace/coverage/default/16.sram_ctrl_regwen.3685970300 Aug 09 06:42:23 PM PDT 24 Aug 09 06:57:06 PM PDT 24 61217933234 ps
T885 /workspace/coverage/default/11.sram_ctrl_partial_access.1109294986 Aug 09 06:41:45 PM PDT 24 Aug 09 06:41:54 PM PDT 24 902637889 ps
T886 /workspace/coverage/default/16.sram_ctrl_executable.1437130660 Aug 09 06:42:24 PM PDT 24 Aug 09 06:55:28 PM PDT 24 5228196969 ps
T887 /workspace/coverage/default/37.sram_ctrl_regwen.3235531713 Aug 09 06:47:24 PM PDT 24 Aug 09 07:01:38 PM PDT 24 8477464775 ps
T888 /workspace/coverage/default/45.sram_ctrl_multiple_keys.3815511952 Aug 09 06:50:06 PM PDT 24 Aug 09 06:56:03 PM PDT 24 37120825459 ps
T889 /workspace/coverage/default/13.sram_ctrl_smoke.3893259773 Aug 09 06:41:50 PM PDT 24 Aug 09 06:42:08 PM PDT 24 1166241898 ps
T890 /workspace/coverage/default/8.sram_ctrl_ram_cfg.3164447742 Aug 09 06:41:36 PM PDT 24 Aug 09 06:41:39 PM PDT 24 1465619714 ps
T891 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1735575138 Aug 09 06:42:18 PM PDT 24 Aug 09 06:59:00 PM PDT 24 14975994880 ps
T892 /workspace/coverage/default/10.sram_ctrl_ram_cfg.4038099658 Aug 09 06:41:37 PM PDT 24 Aug 09 06:41:41 PM PDT 24 358633862 ps
T893 /workspace/coverage/default/0.sram_ctrl_stress_all.3734299262 Aug 09 06:41:05 PM PDT 24 Aug 09 08:52:05 PM PDT 24 268616422780 ps
T894 /workspace/coverage/default/39.sram_ctrl_multiple_keys.2833759605 Aug 09 06:47:57 PM PDT 24 Aug 09 07:09:04 PM PDT 24 52228234980 ps
T895 /workspace/coverage/default/17.sram_ctrl_max_throughput.627807467 Aug 09 06:42:32 PM PDT 24 Aug 09 06:43:55 PM PDT 24 3098217442 ps
T896 /workspace/coverage/default/33.sram_ctrl_multiple_keys.3711660977 Aug 09 06:46:17 PM PDT 24 Aug 09 06:52:29 PM PDT 24 7218909420 ps
T897 /workspace/coverage/default/14.sram_ctrl_max_throughput.2772872484 Aug 09 06:42:02 PM PDT 24 Aug 09 06:44:33 PM PDT 24 801656707 ps
T898 /workspace/coverage/default/1.sram_ctrl_max_throughput.1851303238 Aug 09 06:41:05 PM PDT 24 Aug 09 06:42:18 PM PDT 24 1554640180 ps
T899 /workspace/coverage/default/16.sram_ctrl_mem_walk.3600013441 Aug 09 06:42:25 PM PDT 24 Aug 09 06:47:33 PM PDT 24 5713361933 ps
T900 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.171882505 Aug 09 06:49:16 PM PDT 24 Aug 09 07:00:04 PM PDT 24 29275563626 ps
T901 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3798066872 Aug 09 06:41:23 PM PDT 24 Aug 09 06:48:24 PM PDT 24 10962017181 ps
T902 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3488893539 Aug 09 06:41:28 PM PDT 24 Aug 09 06:42:18 PM PDT 24 6925939241 ps
T903 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.35104447 Aug 09 06:42:25 PM PDT 24 Aug 09 06:52:20 PM PDT 24 8430234908 ps
T904 /workspace/coverage/default/14.sram_ctrl_mem_walk.783004206 Aug 09 06:42:01 PM PDT 24 Aug 09 06:44:33 PM PDT 24 5478784971 ps
T905 /workspace/coverage/default/40.sram_ctrl_stress_all.1995558500 Aug 09 06:48:48 PM PDT 24 Aug 09 08:38:23 PM PDT 24 43711089592 ps
T906 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1106007108 Aug 09 06:41:17 PM PDT 24 Aug 09 06:42:57 PM PDT 24 16062827341 ps
T907 /workspace/coverage/default/43.sram_ctrl_stress_all.4165365888 Aug 09 06:49:49 PM PDT 24 Aug 09 08:28:51 PM PDT 24 187892142489 ps
T908 /workspace/coverage/default/29.sram_ctrl_bijection.282020700 Aug 09 06:45:08 PM PDT 24 Aug 09 07:10:09 PM PDT 24 22206436059 ps
T909 /workspace/coverage/default/7.sram_ctrl_bijection.854367839 Aug 09 06:41:29 PM PDT 24 Aug 09 06:49:32 PM PDT 24 28728235641 ps
T910 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2904084003 Aug 09 06:44:46 PM PDT 24 Aug 09 06:44:49 PM PDT 24 1685577468 ps
T911 /workspace/coverage/default/34.sram_ctrl_alert_test.2355935306 Aug 09 06:46:42 PM PDT 24 Aug 09 06:46:43 PM PDT 24 19724827 ps
T912 /workspace/coverage/default/19.sram_ctrl_alert_test.3189232125 Aug 09 06:43:03 PM PDT 24 Aug 09 06:43:04 PM PDT 24 60363637 ps
T913 /workspace/coverage/default/20.sram_ctrl_mem_walk.537413559 Aug 09 06:43:11 PM PDT 24 Aug 09 06:48:12 PM PDT 24 23869186806 ps
T914 /workspace/coverage/default/2.sram_ctrl_regwen.1604309066 Aug 09 06:41:11 PM PDT 24 Aug 09 06:59:52 PM PDT 24 14458658314 ps
T915 /workspace/coverage/default/30.sram_ctrl_lc_escalation.1787337164 Aug 09 06:45:26 PM PDT 24 Aug 09 06:45:51 PM PDT 24 12566398218 ps
T916 /workspace/coverage/default/9.sram_ctrl_executable.126209210 Aug 09 06:41:37 PM PDT 24 Aug 09 07:01:49 PM PDT 24 76469117648 ps
T917 /workspace/coverage/default/23.sram_ctrl_stress_all.1103242166 Aug 09 06:43:52 PM PDT 24 Aug 09 07:12:03 PM PDT 24 113273231135 ps
T918 /workspace/coverage/default/2.sram_ctrl_executable.2296467975 Aug 09 06:41:12 PM PDT 24 Aug 09 06:52:48 PM PDT 24 11805664753 ps
T919 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2399794429 Aug 09 06:41:18 PM PDT 24 Aug 09 06:50:04 PM PDT 24 8372731562 ps
T920 /workspace/coverage/default/34.sram_ctrl_executable.1966946393 Aug 09 06:46:34 PM PDT 24 Aug 09 06:51:47 PM PDT 24 11183518221 ps
T921 /workspace/coverage/default/18.sram_ctrl_smoke.908522022 Aug 09 06:42:40 PM PDT 24 Aug 09 06:42:47 PM PDT 24 1330295268 ps
T922 /workspace/coverage/default/26.sram_ctrl_mem_walk.1623077177 Aug 09 06:44:28 PM PDT 24 Aug 09 06:49:38 PM PDT 24 21873643934 ps
T923 /workspace/coverage/default/28.sram_ctrl_max_throughput.3239009006 Aug 09 06:44:55 PM PDT 24 Aug 09 06:45:08 PM PDT 24 697020193 ps
T924 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3648771329 Aug 09 06:41:32 PM PDT 24 Aug 09 06:58:17 PM PDT 24 10660002155 ps
T925 /workspace/coverage/default/45.sram_ctrl_regwen.3429850104 Aug 09 06:50:06 PM PDT 24 Aug 09 07:06:48 PM PDT 24 24621931341 ps
T926 /workspace/coverage/default/8.sram_ctrl_multiple_keys.476968426 Aug 09 06:41:34 PM PDT 24 Aug 09 06:55:46 PM PDT 24 237572172922 ps
T927 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.258552587 Aug 09 06:41:29 PM PDT 24 Aug 09 06:44:48 PM PDT 24 3280464530 ps
T928 /workspace/coverage/default/18.sram_ctrl_executable.4256258427 Aug 09 06:42:47 PM PDT 24 Aug 09 06:46:03 PM PDT 24 13813881611 ps
T929 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1157825192 Aug 09 06:44:23 PM PDT 24 Aug 09 06:49:27 PM PDT 24 49084657493 ps
T930 /workspace/coverage/default/35.sram_ctrl_partial_access.204514716 Aug 09 06:46:48 PM PDT 24 Aug 09 06:47:12 PM PDT 24 8812833154 ps
T931 /workspace/coverage/default/4.sram_ctrl_alert_test.3110941137 Aug 09 06:41:20 PM PDT 24 Aug 09 06:41:21 PM PDT 24 64529342 ps
T932 /workspace/coverage/default/44.sram_ctrl_executable.354623868 Aug 09 06:49:49 PM PDT 24 Aug 09 07:03:12 PM PDT 24 48032200134 ps
T933 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3107459983 Aug 09 06:42:39 PM PDT 24 Aug 09 06:48:17 PM PDT 24 34199889618 ps
T934 /workspace/coverage/default/32.sram_ctrl_executable.2671710480 Aug 09 06:46:00 PM PDT 24 Aug 09 07:00:17 PM PDT 24 45040002864 ps
T935 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3308222377 Aug 09 06:42:08 PM PDT 24 Aug 09 06:43:52 PM PDT 24 3337750796 ps
T936 /workspace/coverage/default/21.sram_ctrl_mem_walk.2784820132 Aug 09 06:43:28 PM PDT 24 Aug 09 06:49:10 PM PDT 24 33935313679 ps
T937 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4122293104 Aug 09 07:14:20 PM PDT 24 Aug 09 07:14:24 PM PDT 24 376638561 ps
T69 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.799079375 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:11 PM PDT 24 12989302 ps
T70 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2578537170 Aug 09 07:14:13 PM PDT 24 Aug 09 07:15:06 PM PDT 24 26257863495 ps
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T938 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3536473045 Aug 09 07:14:12 PM PDT 24 Aug 09 07:14:16 PM PDT 24 670473694 ps
T76 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.224281294 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:20 PM PDT 24 83620271 ps
T77 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1609019811 Aug 09 07:14:13 PM PDT 24 Aug 09 07:14:13 PM PDT 24 38501353 ps
T939 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4109507136 Aug 09 07:14:13 PM PDT 24 Aug 09 07:14:17 PM PDT 24 396105928 ps
T940 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2583493094 Aug 09 07:14:29 PM PDT 24 Aug 09 07:14:33 PM PDT 24 358624137 ps
T941 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2865472900 Aug 09 07:14:12 PM PDT 24 Aug 09 07:14:16 PM PDT 24 563502222 ps
T133 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2345253668 Aug 09 07:14:08 PM PDT 24 Aug 09 07:14:09 PM PDT 24 14410875 ps
T78 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4094023095 Aug 09 07:14:07 PM PDT 24 Aug 09 07:14:08 PM PDT 24 30030921 ps
T79 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2078947798 Aug 09 07:14:12 PM PDT 24 Aug 09 07:15:03 PM PDT 24 7047793125 ps
T80 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3713621519 Aug 09 07:14:18 PM PDT 24 Aug 09 07:14:19 PM PDT 24 15386749 ps
T66 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.550254443 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:21 PM PDT 24 159019051 ps
T67 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3553535043 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:13 PM PDT 24 179277195 ps
T100 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1264719624 Aug 09 07:14:02 PM PDT 24 Aug 09 07:14:03 PM PDT 24 22999593 ps
T81 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2341913219 Aug 09 07:14:15 PM PDT 24 Aug 09 07:14:45 PM PDT 24 16184223218 ps
T82 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2659579506 Aug 09 07:14:12 PM PDT 24 Aug 09 07:14:13 PM PDT 24 25572837 ps
T101 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3057692744 Aug 09 07:14:09 PM PDT 24 Aug 09 07:14:10 PM PDT 24 296343273 ps
T942 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.322875355 Aug 09 07:14:14 PM PDT 24 Aug 09 07:14:18 PM PDT 24 368063603 ps
T943 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1218328613 Aug 09 07:14:03 PM PDT 24 Aug 09 07:14:05 PM PDT 24 120879323 ps
T944 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2010312003 Aug 09 07:13:57 PM PDT 24 Aug 09 07:14:01 PM PDT 24 729261388 ps
T102 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.157276641 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:12 PM PDT 24 14864491 ps
T83 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.726811418 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:51 PM PDT 24 16084344538 ps
T945 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3188066724 Aug 09 07:14:20 PM PDT 24 Aug 09 07:14:21 PM PDT 24 18906809 ps
T946 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1197111251 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:11 PM PDT 24 43855953 ps
T947 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.269187839 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:20 PM PDT 24 44832400 ps
T948 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1418442335 Aug 09 07:14:07 PM PDT 24 Aug 09 07:14:09 PM PDT 24 101129444 ps
T949 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.581601912 Aug 09 07:14:17 PM PDT 24 Aug 09 07:14:19 PM PDT 24 29730663 ps
T86 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.760865121 Aug 09 07:13:59 PM PDT 24 Aug 09 07:14:26 PM PDT 24 14774891032 ps
T87 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4277219910 Aug 09 07:14:04 PM PDT 24 Aug 09 07:14:05 PM PDT 24 15626954 ps
T88 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.417616459 Aug 09 07:14:08 PM PDT 24 Aug 09 07:14:39 PM PDT 24 14736920016 ps
T950 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1334565656 Aug 09 07:14:13 PM PDT 24 Aug 09 07:14:17 PM PDT 24 579648692 ps
T951 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1551355606 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:14 PM PDT 24 4854925475 ps
T952 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4172036713 Aug 09 07:14:14 PM PDT 24 Aug 09 07:14:15 PM PDT 24 20248430 ps
T953 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1336179334 Aug 09 07:14:21 PM PDT 24 Aug 09 07:14:25 PM PDT 24 81094601 ps
T954 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1937510424 Aug 09 07:14:16 PM PDT 24 Aug 09 07:14:20 PM PDT 24 1491459968 ps
T68 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.939821851 Aug 09 07:14:20 PM PDT 24 Aug 09 07:14:21 PM PDT 24 347001626 ps
T955 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.852554582 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:13 PM PDT 24 1413921846 ps
T956 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.676185242 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:20 PM PDT 24 83608540 ps
T957 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3452957619 Aug 09 07:14:16 PM PDT 24 Aug 09 07:14:20 PM PDT 24 248986220 ps
T958 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.642369583 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:47 PM PDT 24 3885284175 ps
T959 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4024242228 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:22 PM PDT 24 521542702 ps
T119 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3457716545 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:12 PM PDT 24 516154501 ps
T126 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3206360775 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:12 PM PDT 24 551058610 ps
T129 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1383532259 Aug 09 07:14:14 PM PDT 24 Aug 09 07:14:17 PM PDT 24 374249613 ps
T960 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3494252543 Aug 09 07:14:03 PM PDT 24 Aug 09 07:14:05 PM PDT 24 357009369 ps
T89 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2919691492 Aug 09 07:14:14 PM PDT 24 Aug 09 07:14:15 PM PDT 24 26446389 ps
T961 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1060976774 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:11 PM PDT 24 18519734 ps
T962 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.176112771 Aug 09 07:14:21 PM PDT 24 Aug 09 07:14:22 PM PDT 24 80132550 ps
T963 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.650425090 Aug 09 07:14:20 PM PDT 24 Aug 09 07:14:54 PM PDT 24 15373360989 ps
T964 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2064607589 Aug 09 07:14:20 PM PDT 24 Aug 09 07:14:22 PM PDT 24 23551156 ps
T122 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.559154673 Aug 09 07:14:13 PM PDT 24 Aug 09 07:14:16 PM PDT 24 520252428 ps
T965 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2028144780 Aug 09 07:14:08 PM PDT 24 Aug 09 07:14:09 PM PDT 24 26845816 ps
T966 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3387992062 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:14 PM PDT 24 356170031 ps
T96 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1891144340 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:38 PM PDT 24 7748078225 ps
T967 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3519298003 Aug 09 07:14:17 PM PDT 24 Aug 09 07:14:19 PM PDT 24 20745289 ps
T131 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3297154463 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:11 PM PDT 24 467164728 ps
T120 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2634844384 Aug 09 07:14:17 PM PDT 24 Aug 09 07:14:19 PM PDT 24 723982435 ps
T968 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3417509095 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:15 PM PDT 24 2190220280 ps
T130 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2004583555 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:21 PM PDT 24 215787069 ps
T97 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2588426450 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:38 PM PDT 24 21975091671 ps
T969 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1153485948 Aug 09 07:14:25 PM PDT 24 Aug 09 07:14:26 PM PDT 24 77406878 ps
T123 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1392556028 Aug 09 07:14:19 PM PDT 24 Aug 09 07:14:22 PM PDT 24 912923592 ps
T127 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3340028781 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:13 PM PDT 24 215769667 ps
T970 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.859187400 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:11 PM PDT 24 22499834 ps
T98 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.939059485 Aug 09 07:14:09 PM PDT 24 Aug 09 07:14:41 PM PDT 24 20462053201 ps
T971 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2627222253 Aug 09 07:14:19 PM PDT 24 Aug 09 07:15:21 PM PDT 24 28196689274 ps
T972 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1659305604 Aug 09 07:14:11 PM PDT 24 Aug 09 07:15:11 PM PDT 24 22007284526 ps
T973 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1203433655 Aug 09 07:14:17 PM PDT 24 Aug 09 07:14:21 PM PDT 24 1481739593 ps
T974 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.349424147 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:12 PM PDT 24 14104480 ps
T975 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.617157870 Aug 09 07:13:59 PM PDT 24 Aug 09 07:14:00 PM PDT 24 31090885 ps
T976 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.538924000 Aug 09 07:14:11 PM PDT 24 Aug 09 07:15:07 PM PDT 24 23566631946 ps
T124 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3082379935 Aug 09 07:14:22 PM PDT 24 Aug 09 07:14:25 PM PDT 24 256694012 ps
T977 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2650662941 Aug 09 07:14:08 PM PDT 24 Aug 09 07:14:08 PM PDT 24 29300579 ps
T978 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1051858087 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:12 PM PDT 24 38375333 ps
T979 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.671437095 Aug 09 07:14:02 PM PDT 24 Aug 09 07:14:05 PM PDT 24 370911644 ps
T980 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2963247292 Aug 09 07:14:10 PM PDT 24 Aug 09 07:14:15 PM PDT 24 161165563 ps
T981 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3023454177 Aug 09 07:14:02 PM PDT 24 Aug 09 07:14:04 PM PDT 24 52149120 ps
T982 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2777474388 Aug 09 07:14:02 PM PDT 24 Aug 09 07:14:03 PM PDT 24 87018640 ps
T983 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2581430655 Aug 09 07:14:23 PM PDT 24 Aug 09 07:14:24 PM PDT 24 106113929 ps
T984 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3458848163 Aug 09 07:14:22 PM PDT 24 Aug 09 07:14:49 PM PDT 24 3863508753 ps
T985 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3143259366 Aug 09 07:14:26 PM PDT 24 Aug 09 07:14:26 PM PDT 24 38543570 ps
T986 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1919318932 Aug 09 07:14:18 PM PDT 24 Aug 09 07:14:22 PM PDT 24 722545222 ps
T987 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.304476749 Aug 09 07:14:15 PM PDT 24 Aug 09 07:14:15 PM PDT 24 41600169 ps
T988 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.349895936 Aug 09 07:14:21 PM PDT 24 Aug 09 07:14:22 PM PDT 24 54851629 ps
T989 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1707799327 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:14 PM PDT 24 46738354 ps
T990 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1705623115 Aug 09 07:14:18 PM PDT 24 Aug 09 07:14:22 PM PDT 24 36323223 ps
T991 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1860641023 Aug 09 07:14:11 PM PDT 24 Aug 09 07:14:12 PM PDT 24 65662520 ps
T992 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2553525462 Aug 09 07:14:17 PM PDT 24 Aug 09 07:14:17 PM PDT 24 34033813 ps
T993 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2846700428 Aug 09 07:14:14 PM PDT 24 Aug 09 07:14:16 PM PDT 24 395226504 ps
T994 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.354555663 Aug 09 07:14:06 PM PDT 24 Aug 09 07:14:08 PM PDT 24 186193815 ps
T121 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.598306042 Aug 09 07:14:07 PM PDT 24 Aug 09 07:14:09 PM PDT 24 184562595 ps
T995 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1233910706 Aug 09 07:14:10 PM PDT 24 Aug 09 07:15:05 PM PDT 24 14497382799 ps
T996 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.334261548 Aug 09 07:14:04 PM PDT 24 Aug 09 07:14:05 PM PDT 24 41969956 ps
T997 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1183480620 Aug 09 07:14:08 PM PDT 24 Aug 09 07:14:09 PM PDT 24 18132043 ps
T998 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2863525594 Aug 09 07:14:09 PM PDT 24 Aug 09 07:14:10 PM PDT 24 52317636 ps
T999 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.732736563 Aug 09 07:14:08 PM PDT 24 Aug 09 07:14:10 PM PDT 24 157702725 ps
T1000 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4110233797 Aug 09 07:14:18 PM PDT 24 Aug 09 07:14:19 PM PDT 24 23924995 ps
T1001 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1489854769 Aug 09 07:14:12 PM PDT 24 Aug 09 07:14:15 PM PDT 24 1417552675 ps
T1002 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.510634144 Aug 09 07:14:21 PM PDT 24 Aug 09 07:14:22 PM PDT 24 13627111 ps
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