Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16370545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153622178

1

T1

252920

T2

157286

T3

157139

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83672758	1			T1	138739		T2	786432		T3	86655
values[0x0]	41523766	1			T1	67365		T2	392341		T3	41634
values[0x1]	44796199	1			T1	72010		T2	394091		T3	44692

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8337105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161655618

1

T1

265633

T2

157286

T3

165125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	576867	1			T1	492		T2	6043		T3	664
valid_sources[0x01]	573629	1			T1	441		T2	6141		T3	671
valid_sources[0x02]	553636	1			T1	476		T2	6374		T3	716
valid_sources[0x03]	752713	1			T1	487		T2	6291		T3	678
valid_sources[0x04]	553914	1			T1	481		T2	6160		T3	711
valid_sources[0x05]	2142857	1			T1	694		T2	6089		T3	670
valid_sources[0x06]	564543	1			T1	672		T2	6317		T3	693
valid_sources[0x07]	560843	1			T1	563		T2	6496		T3	711
valid_sources[0x08]	558591	1			T1	8774		T2	6170		T3	717
valid_sources[0x09]	543012	1			T1	617		T2	6237		T3	643
valid_sources[0x0a]	1287340	1			T1	6184		T2	6118		T3	709
valid_sources[0x0b]	622953	1			T1	431		T2	6029		T3	702
valid_sources[0x0c]	579445	1			T1	457		T2	6058		T3	681
valid_sources[0x0d]	599770	1			T1	456		T2	6046		T3	663
valid_sources[0x0e]	567933	1			T1	462		T2	6172		T3	697
valid_sources[0x0f]	647647	1			T1	513		T2	6180		T3	677
valid_sources[0x10]	585254	1			T1	453		T2	6104		T3	672
valid_sources[0x11]	549039	1			T1	528		T2	6263		T3	669
valid_sources[0x12]	541884	1			T1	537		T2	6141		T3	702
valid_sources[0x13]	585551	1			T1	552		T2	6118		T3	675
valid_sources[0x14]	542048	1			T1	424		T2	6182		T3	669
valid_sources[0x15]	576684	1			T1	426		T2	6068		T3	678
valid_sources[0x16]	672025	1			T1	489		T2	6189		T3	672
valid_sources[0x17]	552407	1			T1	532		T2	6305		T3	667
valid_sources[0x18]	602788	1			T1	466		T2	5948		T3	682
valid_sources[0x19]	561265	1			T1	436		T2	5899		T3	735
valid_sources[0x1a]	548182	1			T1	375		T2	6329		T3	705
valid_sources[0x1b]	549635	1			T1	400		T2	6238		T3	663
valid_sources[0x1c]	552292	1			T1	634		T2	6330		T3	714
valid_sources[0x1d]	579779	1			T1	621		T2	6310		T3	694
valid_sources[0x1e]	600307	1			T1	479		T2	6307		T3	712
valid_sources[0x1f]	560701	1			T1	440		T2	6216		T3	688
valid_sources[0x20]	552168	1			T1	598		T2	6223		T3	682
valid_sources[0x21]	554481	1			T1	540		T2	6394		T3	681
valid_sources[0x22]	550179	1			T1	487		T2	6175		T3	676
valid_sources[0x23]	596478	1			T1	538		T2	6097		T3	669
valid_sources[0x24]	553719	1			T1	609		T2	6293		T3	659
valid_sources[0x25]	592857	1			T1	592		T2	6140		T3	622
valid_sources[0x26]	614965	1			T1	567		T2	6259		T3	648
valid_sources[0x27]	550638	1			T1	489		T2	6131		T3	672
valid_sources[0x28]	591382	1			T1	8601		T2	6045		T3	706
valid_sources[0x29]	572687	1			T1	548		T2	6395		T3	649
valid_sources[0x2a]	548820	1			T1	429		T2	6119		T3	600
valid_sources[0x2b]	622182	1			T1	407		T2	5987		T3	688
valid_sources[0x2c]	636550	1			T1	556		T2	6113		T3	730
valid_sources[0x2d]	582355	1			T1	535		T2	6142		T3	688
valid_sources[0x2e]	540792	1			T1	655		T2	6013		T3	692
valid_sources[0x2f]	566072	1			T1	653		T2	6230		T3	658
valid_sources[0x30]	551470	1			T1	492		T2	6068		T3	662
valid_sources[0x31]	545860	1			T1	511		T2	6154		T3	693
valid_sources[0x32]	541371	1			T1	551		T2	5956		T3	637
valid_sources[0x33]	549704	1			T1	503		T2	6263		T3	649
valid_sources[0x34]	558466	1			T1	564		T2	6082		T3	656
valid_sources[0x35]	562415	1			T1	570		T2	6091		T3	690
valid_sources[0x36]	1797863	1			T1	492		T2	6067		T3	682
valid_sources[0x37]	1251527	1			T1	410		T2	5968		T3	626
valid_sources[0x38]	540181	1			T1	471		T2	6126		T3	631
valid_sources[0x39]	599839	1			T1	507		T2	6063		T3	638
valid_sources[0x3a]	551268	1			T1	561		T2	6098		T3	703
valid_sources[0x3b]	549146	1			T1	437		T2	5970		T3	689
valid_sources[0x3c]	552323	1			T1	581		T2	5984		T3	663
valid_sources[0x3d]	578524	1			T1	462		T2	5955		T3	682
valid_sources[0x3e]	937350	1			T1	442		T2	6325		T3	618
valid_sources[0x3f]	585850	1			T1	496		T2	6044		T3	671
valid_sources[0x40]	564507	1			T1	582		T2	6102		T3	622
valid_sources[0x41]	565629	1			T1	631		T2	6390		T3	631
valid_sources[0x42]	564404	1			T1	570		T2	6116		T3	677
valid_sources[0x43]	571153	1			T1	507		T2	6241		T3	701
valid_sources[0x44]	1398899	1			T1	566		T2	6298		T3	692
valid_sources[0x45]	575952	1			T1	376		T2	5841		T3	632
valid_sources[0x46]	563274	1			T1	546		T2	6262		T3	669
valid_sources[0x47]	676641	1			T1	400		T2	6188		T3	723
valid_sources[0x48]	570609	1			T1	538		T2	6126		T3	674
valid_sources[0x49]	557371	1			T1	626		T2	6215		T3	677
valid_sources[0x4a]	867402	1			T1	552		T2	6177		T3	670
valid_sources[0x4b]	3007300	1			T1	395		T2	6092		T3	679
valid_sources[0x4c]	1207580	1			T1	593		T2	6227		T3	665
valid_sources[0x4d]	572976	1			T1	562		T2	6053		T3	623
valid_sources[0x4e]	537008	1			T1	471		T2	6321		T3	701
valid_sources[0x4f]	561628	1			T1	521		T2	6125		T3	660
valid_sources[0x50]	556970	1			T1	469		T2	6129		T3	654
valid_sources[0x51]	757258	1			T1	526		T2	6126		T3	697
valid_sources[0x52]	554160	1			T1	452		T2	6030		T3	665
valid_sources[0x53]	1416523	1			T1	633		T2	5996		T3	650
valid_sources[0x54]	542793	1			T1	551		T2	6198		T3	699
valid_sources[0x55]	542062	1			T1	539		T2	5922		T3	704
valid_sources[0x56]	574445	1			T1	409		T2	6237		T3	698
valid_sources[0x57]	548893	1			T1	499		T2	6184		T3	645
valid_sources[0x58]	544861	1			T1	499		T2	6135		T3	699
valid_sources[0x59]	538210	1			T1	426		T2	6217		T3	664
valid_sources[0x5a]	564058	1			T1	443		T2	6238		T3	681
valid_sources[0x5b]	540759	1			T1	604		T2	6236		T3	639
valid_sources[0x5c]	550583	1			T1	515		T2	5993		T3	660
valid_sources[0x5d]	573750	1			T1	563		T2	6103		T3	654
valid_sources[0x5e]	571501	1			T1	436		T2	6077		T3	661
valid_sources[0x5f]	544626	1			T1	515		T2	6305		T3	701
valid_sources[0x60]	562122	1			T1	561		T2	6081		T3	711
valid_sources[0x61]	592952	1			T1	574		T2	6000		T3	729
valid_sources[0x62]	577249	1			T1	444		T2	6425		T3	693
valid_sources[0x63]	548558	1			T1	589		T2	6103		T3	647
valid_sources[0x64]	569301	1			T1	500		T2	5773		T3	700
valid_sources[0x65]	559893	1			T1	461		T2	5953		T3	660
valid_sources[0x66]	549031	1			T1	472		T2	6230		T3	655
valid_sources[0x67]	615542	1			T1	26959		T2	6196		T3	620
valid_sources[0x68]	557409	1			T1	478		T2	6323		T3	713
valid_sources[0x69]	570445	1			T1	513		T2	6218		T3	654
valid_sources[0x6a]	581426	1			T1	421		T2	6188		T3	693
valid_sources[0x6b]	1431621	1			T1	454		T2	6031		T3	694
valid_sources[0x6c]	638518	1			T1	559		T2	6240		T3	691
valid_sources[0x6d]	553231	1			T1	555		T2	6150		T3	675
valid_sources[0x6e]	553467	1			T1	525		T2	6037		T3	734
valid_sources[0x6f]	584023	1			T1	485		T2	6112		T3	642
valid_sources[0x70]	659199	1			T1	505		T2	6069		T3	672
valid_sources[0x71]	1532068	1			T1	517		T2	6072		T3	701
valid_sources[0x72]	737282	1			T1	434		T2	6221		T3	640
valid_sources[0x73]	547355	1			T1	455		T2	5943		T3	663
valid_sources[0x74]	609028	1			T1	9455		T2	6167		T3	703
valid_sources[0x75]	562675	1			T1	468		T2	6045		T3	684
valid_sources[0x76]	599831	1			T1	554		T2	6134		T3	652
valid_sources[0x77]	558012	1			T1	517		T2	6276		T3	668
valid_sources[0x78]	561708	1			T1	7349		T2	6439		T3	753
valid_sources[0x79]	547469	1			T1	493		T2	6169		T3	684
valid_sources[0x7a]	580927	1			T1	606		T2	6044		T3	679
valid_sources[0x7b]	1066321	1			T1	467		T2	6059		T3	679
valid_sources[0x7c]	749317	1			T1	459		T2	6243		T3	680
valid_sources[0x7d]	565112	1			T1	436		T2	6131		T3	687
valid_sources[0x7e]	548588	1			T1	615		T2	6231		T3	652
valid_sources[0x7f]	602752	1			T1	627		T2	6128		T3	674
valid_sources[0x80]	547856	1			T1	504		T2	6227		T3	699

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75444015

1

T1

126127

T2

786432

T3

78742

values[0x0]

all_enables

biggest_size

39082525

1

T1

63599

T2

392341

T3

39307

values[0x1]

all_enables

biggest_size

39095638

1

T1

63194

T2

394091

T3

39090

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

160315

1

T1

7

T2

7

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57182	1			T1	6		T3	16		T4	28
values[0x0]	72275	1			T1	16		T2	15		T3	40
values[0x1]	77146	1			T1	18		T2	9		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

170878

1

T1

11

T2

9

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	872	1			T20	3		T21	10		T33	1
valid_sources[0x01]	690	1			T90	1		T20	9		T21	12
valid_sources[0x02]	694	1			T21	20		T15	1		T142	6
valid_sources[0x03]	873	1			T3	4		T17	3		T20	12
valid_sources[0x04]	711	1			T20	4		T21	28		T43	9
valid_sources[0x05]	789	1			T37	1		T20	1		T21	23
valid_sources[0x06]	1003	1			T141	1		T39	1		T20	19
valid_sources[0x07]	635	1			T9	1		T20	18		T21	27
valid_sources[0x08]	628	1			T20	1		T21	15		T33	1
valid_sources[0x09]	972	1			T20	41		T21	10		T15	1
valid_sources[0x0a]	675	1			T20	8		T21	14		T142	2
valid_sources[0x0b]	587	1			T3	2		T5	1		T20	14
valid_sources[0x0c]	672	1			T20	8		T21	23		T143	2
valid_sources[0x0d]	692	1			T20	7		T21	16		T33	1
valid_sources[0x0e]	703	1			T5	2		T36	1		T20	9
valid_sources[0x0f]	734	1			T2	1		T34	1		T38	1
valid_sources[0x10]	852	1			T2	1		T5	1		T20	9
valid_sources[0x11]	661	1			T20	4		T21	10		T33	2
valid_sources[0x12]	1023	1			T2	1		T3	1		T17	8
valid_sources[0x13]	695	1			T3	1		T140	16		T39	1
valid_sources[0x14]	1061	1			T141	1		T20	4		T21	16
valid_sources[0x15]	1073	1			T2	1		T20	20		T21	28
valid_sources[0x16]	805	1			T50	1		T20	36		T21	25
valid_sources[0x17]	651	1			T144	1		T20	1		T21	8
valid_sources[0x18]	727	1			T141	1		T20	16		T21	27
valid_sources[0x19]	1042	1			T20	1		T21	21		T43	9
valid_sources[0x1a]	1443	1			T4	4		T141	1		T20	4
valid_sources[0x1b]	989	1			T2	1		T141	1		T20	21
valid_sources[0x1c]	836	1			T35	1		T20	1		T21	15
valid_sources[0x1d]	1004	1			T20	4		T21	17		T15	1
valid_sources[0x1e]	679	1			T52	2		T20	2		T21	26
valid_sources[0x1f]	753	1			T20	1		T21	24		T33	3
valid_sources[0x20]	1048	1			T20	6		T29	1		T21	21
valid_sources[0x21]	565	1			T2	1		T8	9		T20	2
valid_sources[0x22]	672	1			T20	10		T21	26		T33	3
valid_sources[0x23]	810	1			T55	1		T20	6		T21	20
valid_sources[0x24]	691	1			T3	2		T23	1		T141	1
valid_sources[0x25]	1332	1			T2	1		T4	2		T20	2
valid_sources[0x26]	586	1			T42	3		T21	19		T43	5
valid_sources[0x27]	843	1			T10	1		T35	2		T39	1
valid_sources[0x28]	668	1			T145	2		T20	6		T21	12
valid_sources[0x29]	772	1			T3	1		T21	25		T33	2
valid_sources[0x2a]	1201	1			T3	1		T17	40		T20	10
valid_sources[0x2b]	866	1			T105	2		T20	21		T21	12
valid_sources[0x2c]	693	1			T21	12		T15	2		T142	3
valid_sources[0x2d]	792	1			T2	1		T10	1		T20	1
valid_sources[0x2e]	641	1			T141	1		T20	8		T21	18
valid_sources[0x2f]	638	1			T3	3		T6	1		T146	3
valid_sources[0x30]	854	1			T35	2		T21	23		T15	1
valid_sources[0x31]	846	1			T39	1		T14	80		T20	20
valid_sources[0x32]	722	1			T5	1		T34	1		T20	11
valid_sources[0x33]	867	1			T34	2		T53	1		T21	22
valid_sources[0x34]	667	1			T53	1		T20	5		T21	18
valid_sources[0x35]	823	1			T37	1		T141	2		T20	27
valid_sources[0x36]	686	1			T20	29		T21	9		T33	1
valid_sources[0x37]	1027	1			T3	1		T20	7		T21	26
valid_sources[0x38]	574	1			T36	1		T141	2		T39	1
valid_sources[0x39]	814	1			T5	1		T35	1		T20	8
valid_sources[0x3a]	622	1			T37	1		T20	11		T29	1
valid_sources[0x3b]	997	1			T3	1		T17	17		T141	1
valid_sources[0x3c]	867	1			T20	10		T21	17		T147	1
valid_sources[0x3d]	706	1			T2	1		T8	5		T56	3
valid_sources[0x3e]	704	1			T8	5		T20	11		T21	17
valid_sources[0x3f]	922	1			T20	1		T21	13		T147	1
valid_sources[0x40]	642	1			T8	2		T20	1		T21	16
valid_sources[0x41]	857	1			T4	3		T20	13		T21	20
valid_sources[0x42]	971	1			T3	1		T20	1		T21	20
valid_sources[0x43]	775	1			T2	1		T3	1		T55	2
valid_sources[0x44]	1285	1			T3	2		T17	1		T21	13
valid_sources[0x45]	670	1			T8	6		T20	7		T29	1
valid_sources[0x46]	889	1			T3	3		T8	9		T5	2
valid_sources[0x47]	1048	1			T20	19		T21	27		T22	68
valid_sources[0x48]	759	1			T21	25		T32	1		T33	1
valid_sources[0x49]	722	1			T34	1		T20	2		T29	1
valid_sources[0x4a]	1034	1			T20	7		T21	28		T43	4
valid_sources[0x4b]	810	1			T5	1		T55	2		T21	11
valid_sources[0x4c]	689	1			T4	2		T5	1		T39	1
valid_sources[0x4d]	672	1			T3	1		T20	5		T21	12
valid_sources[0x4e]	959	1			T41	3		T20	3		T21	9
valid_sources[0x4f]	635	1			T2	1		T3	1		T141	1
valid_sources[0x50]	778	1			T20	2		T21	10		T147	1
valid_sources[0x51]	540	1			T20	4		T21	18		T142	3
valid_sources[0x52]	820	1			T4	3		T6	5		T20	25
valid_sources[0x53]	814	1			T4	14		T8	3		T17	5
valid_sources[0x54]	1095	1			T37	2		T20	12		T21	18
valid_sources[0x55]	609	1			T4	11		T34	1		T20	20
valid_sources[0x56]	792	1			T20	6		T21	20		T33	1
valid_sources[0x57]	1070	1			T2	1		T3	2		T7	1
valid_sources[0x58]	862	1			T5	1		T144	3		T20	13
valid_sources[0x59]	833	1			T20	27		T21	16		T33	1
valid_sources[0x5a]	849	1			T3	2		T90	1		T20	24
valid_sources[0x5b]	1264	1			T37	1		T20	23		T21	8
valid_sources[0x5c]	673	1			T2	1		T4	3		T37	1
valid_sources[0x5d]	891	1			T8	3		T37	1		T20	20
valid_sources[0x5e]	743	1			T5	1		T30	37		T21	10
valid_sources[0x5f]	938	1			T135	30		T20	4		T21	23
valid_sources[0x60]	545	1			T20	4		T21	18		T33	1
valid_sources[0x61]	840	1			T3	2		T20	13		T21	15
valid_sources[0x62]	862	1			T5	1		T35	1		T17	24
valid_sources[0x63]	629	1			T8	3		T20	1		T21	13
valid_sources[0x64]	828	1			T5	1		T20	3		T21	19
valid_sources[0x65]	908	1			T35	3		T20	6		T21	22
valid_sources[0x66]	806	1			T2	1		T5	1		T37	1
valid_sources[0x67]	822	1			T20	8		T21	15		T148	2
valid_sources[0x68]	668	1			T35	1		T141	1		T20	1
valid_sources[0x69]	654	1			T8	8		T35	2		T20	8
valid_sources[0x6a]	1020	1			T141	1		T20	9		T21	18
valid_sources[0x6b]	628	1			T3	2		T20	7		T21	12
valid_sources[0x6c]	741	1			T5	1		T21	15		T149	1
valid_sources[0x6d]	670	1			T17	3		T20	2		T21	10
valid_sources[0x6e]	764	1			T35	3		T21	5		T15	1
valid_sources[0x6f]	787	1			T144	1		T21	17		T33	2
valid_sources[0x70]	888	1			T20	3		T21	17		T147	1
valid_sources[0x71]	733	1			T20	9		T21	17		T43	3
valid_sources[0x72]	479	1			T20	8		T21	10		T33	1
valid_sources[0x73]	612	1			T9	1		T21	23		T143	3
valid_sources[0x74]	860	1			T35	1		T36	1		T20	23
valid_sources[0x75]	1046	1			T144	1		T20	14		T21	21
valid_sources[0x76]	703	1			T20	8		T21	15		T149	1
valid_sources[0x77]	712	1			T37	2		T20	2		T21	15
valid_sources[0x78]	834	1			T150	2		T20	33		T21	27
valid_sources[0x79]	908	1			T3	1		T20	22		T21	11
valid_sources[0x7a]	880	1			T3	2		T4	1		T20	4
valid_sources[0x7b]	617	1			T8	3		T17	1		T20	8
valid_sources[0x7c]	1105	1			T3	2		T20	11		T21	16
valid_sources[0x7d]	785	1			T3	2		T40	30		T20	12
valid_sources[0x7e]	685	1			T35	5		T21	17		T33	1
valid_sources[0x7f]	741	1			T8	22		T20	11		T21	27
valid_sources[0x80]	1043	1			T34	1		T20	2		T21	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43230

1

T1

2

T3

8

T4

16

values[0x0]

all_enables

biggest_size

60211

1

T1

2

T2

4

T3

12

values[0x1]

all_enables

biggest_size

56874

1

T1

3

T2

3

T3

5