Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16276601

1

T1

24200

T3

13837

T4

96

full_word

150493202

1

T1

243429

T2

157286

T3

137198

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166769503	1			T1	267629		T2	157286		T3	151035
auto[TlIntgErrCmd]	90	1			T62	6		T63	8		T64	6
auto[TlIntgErrData]	112	1			T62	9		T63	9		T64	4
auto[TlIntgErrBoth]	98	1			T62	5		T63	3		T64	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80359723

1

T1

128481

T2

786432

T3

64709

auto[1]

86410080

1

T1

139148

T2

786432

T3

86326

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7968208	1			T1	11644		T3	5908		T4	52
auto[TlIntgErrNone]	partial	auto[1]	8308116	1			T1	12556		T3	7929		T4	44
auto[TlIntgErrNone]	full_word	auto[0]	72391385	1			T1	116837		T2	786432		T3	58801
auto[TlIntgErrNone]	full_word	auto[1]	78101794	1			T1	126592		T2	786432		T3	78397
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T62	2		T63	1		T64	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T62	3		T63	5		T64	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T129	1		T130	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T62	1		T63	2		T131	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T62	5		T63	7		T64	1
auto[TlIntgErrData]	partial	auto[1]	58	1			T62	3		T63	1		T64	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T131	1		T129	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T62	1		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T62	1		T63	2		T64	5
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T62	3		T63	1		T64	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T131	1		T127	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T62	1		T134	1		-	-