Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	859892	1			T1	13422		T35	1210		T17	24859
auto[1]	10994046	1			T1	3229		T3	12135		T4	449
auto[2]	662774	1			T1	11835		T8	1		T35	654
auto[3]	10675307	1			T1	1853		T3	7498		T4	436

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14792215	1			T1	23971		T3	16195		T4	741
auto[1]	2135474	1			T1	3233		T3	1618		T4	62
auto[2]	2175896	1			T1	2801		T3	1672		T4	77
auto[3]	4088434	1			T1	334		T3	148		T4	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9819892

1

T1

30338

T3

19632

T4

885

auto[1]

13372127

1

T1

1

T3

1

T8

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	276551	1			T1	11092		T35	1020		T17	20646
auto[0]	auto[0]	auto[1]	29185	1			T1	1090		T35	87		T17	2010
auto[0]	auto[0]	auto[2]	29225	1			T1	1132		T35	95		T17	1998
auto[0]	auto[0]	auto[3]	54268	1			T1	108		T35	8		T17	204
auto[0]	auto[1]	auto[0]	3530258	1			T1	1845		T3	10025		T4	374
auto[0]	auto[1]	auto[1]	362009	1			T1	1107		T3	987		T4	27
auto[0]	auto[1]	auto[2]	388505	1			T1	167		T3	1034		T4	47
auto[0]	auto[1]	auto[3]	402304	1			T1	110		T3	88		T4	1
auto[0]	auto[2]	auto[0]	197874	1			T1	10099		T8	1		T35	487
auto[0]	auto[2]	auto[1]	23899	1			T1	955		T35	72		T17	1446
auto[0]	auto[2]	auto[2]	23713	1			T1	718		T35	90		T17	1184
auto[0]	auto[2]	auto[3]	42529	1			T1	62		T35	5		T17	114
auto[0]	auto[3]	auto[0]	3347644	1			T1	935		T3	6170		T4	367
auto[0]	auto[3]	auto[1]	367254	1			T1	81		T3	630		T4	35
auto[0]	auto[3]	auto[2]	374832	1			T1	783		T3	638		T4	30
auto[0]	auto[3]	auto[3]	369842	1			T1	54		T3	60		T4	4
auto[1]	auto[0]	auto[0]	15546	1			T17	1		T55	818		T104	84
auto[1]	auto[0]	auto[1]	69928	1			T55	3619		T104	436		T74	3940
auto[1]	auto[0]	auto[2]	70110	1			T55	3555		T104	409		T74	3896
auto[1]	auto[0]	auto[3]	315079	1			T55	15976		T104	1901		T74	17837
auto[1]	auto[1]	auto[0]	3709369	1			T8	2		T10	55857		T18	1
auto[1]	auto[1]	auto[1]	640597	1			T3	1		T10	4881		T55	3481
auto[1]	auto[1]	auto[2]	606587	1			T10	5463		T55	567		T104	738
auto[1]	auto[1]	auto[3]	1354417	1			T10	520		T55	16203		T90	1
auto[1]	auto[2]	auto[0]	11814	1			T55	716		T27	1		T74	805
auto[1]	auto[2]	auto[1]	52291	1			T55	3312		T74	3719		T107	3939
auto[1]	auto[2]	auto[2]	56475	1			T1	1		T55	3016		T104	394
auto[1]	auto[2]	auto[3]	254179	1			T55	13576		T104	1706		T74	11993
auto[1]	auto[3]	auto[0]	3703159	1			T10	55875		T55	56		T104	69
auto[1]	auto[3]	auto[1]	590311	1			T10	5473		T55	270		T104	338
auto[1]	auto[3]	auto[2]	626449	1			T10	5000		T55	3094		T104	1366
auto[1]	auto[3]	auto[3]	1295816	1			T10	486		T55	13380		T104	6140