Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1079794745	234952	0	0
ctrl_regwen_rd_A	1079794745	5209	0	0
exec_rd_A	1079794745	5229	0	0
exec_regwen_rd_A	1079794745	5237	0	0
readback_rd_A	1079794745	3569	0	0
readback_regwen_rd_A	1079794745	3356	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079794745	234952	0	0
T20	99893	4063	0	0
T21	140493	7850	0	0
T22	0	2840	0	0
T28	452543	0	0	0
T29	475506	0	0	0
T30	153871	0	0	0
T31	487873	0	0	0
T32	295574	0	0	0
T33	400825	0	0	0
T43	0	3176	0	0
T57	0	4471	0	0
T69	0	1911	0	0
T70	0	1846	0	0
T71	0	1659	0	0
T72	0	3043	0	0
T73	0	4473	0	0
T74	203706	0	0	0
T75	113114	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079794745	5209	0	0
T43	70022	139	0	0
T48	179607	0	0	0
T61	0	214	0	0
T69	0	103	0	0
T110	0	138	0	0
T111	0	99	0	0
T112	0	240	0	0
T113	0	353	0	0
T114	0	141	0	0
T115	0	233	0	0
T116	0	321	0	0
T117	906252	0	0	0
T118	955118	0	0	0
T119	34072	0	0	0
T120	160653	0	0	0
T121	116901	0	0	0
T122	403498	0	0	0
T123	83464	0	0	0
T124	190779	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079794745	5229	0	0
T43	70022	109	0	0
T48	179607	0	0	0
T61	0	207	0	0
T69	0	116	0	0
T110	0	218	0	0
T111	0	125	0	0
T112	0	186	0	0
T113	0	258	0	0
T114	0	125	0	0
T115	0	227	0	0
T116	0	387	0	0
T117	906252	0	0	0
T118	955118	0	0	0
T119	34072	0	0	0
T120	160653	0	0	0
T121	116901	0	0	0
T122	403498	0	0	0
T123	83464	0	0	0
T124	190779	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079794745	5237	0	0
T43	70022	158	0	0
T48	179607	0	0	0
T61	0	239	0	0
T69	0	130	0	0
T110	0	191	0	0
T111	0	74	0	0
T112	0	282	0	0
T113	0	254	0	0
T114	0	170	0	0
T115	0	165	0	0
T116	0	365	0	0
T117	906252	0	0	0
T118	955118	0	0	0
T119	34072	0	0	0
T120	160653	0	0	0
T121	116901	0	0	0
T122	403498	0	0	0
T123	83464	0	0	0
T124	190779	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079794745	3569	0	0
T43	70022	43	0	0
T48	179607	0	0	0
T61	0	274	0	0
T69	0	90	0	0
T110	0	187	0	0
T111	0	70	0	0
T112	0	261	0	0
T113	0	288	0	0
T114	0	114	0	0
T115	0	265	0	0
T116	0	336	0	0
T117	906252	0	0	0
T118	955118	0	0	0
T119	34072	0	0	0
T120	160653	0	0	0
T121	116901	0	0	0
T122	403498	0	0	0
T123	83464	0	0	0
T124	190779	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079794745	3356	0	0
T43	70022	121	0	0
T48	179607	0	0	0
T61	0	187	0	0
T69	0	128	0	0
T110	0	245	0	0
T111	0	66	0	0
T112	0	152	0	0
T113	0	254	0	0
T114	0	135	0	0
T115	0	283	0	0
T116	0	266	0	0
T117	906252	0	0	0
T118	955118	0	0	0
T119	34072	0	0	0
T120	160653	0	0	0
T121	116901	0	0	0
T122	403498	0	0	0
T123	83464	0	0	0
T124	190779	0	0	0