| T791 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.941998977 |
|
|
Aug 10 05:34:10 PM PDT 24 |
Aug 10 05:37:22 PM PDT 24 |
6096343221 ps |
| T792 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1546877741 |
|
|
Aug 10 05:30:28 PM PDT 24 |
Aug 10 05:31:28 PM PDT 24 |
19075890529 ps |
| T793 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.996243600 |
|
|
Aug 10 05:32:52 PM PDT 24 |
Aug 10 05:35:13 PM PDT 24 |
1605499935 ps |
| T794 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3340844543 |
|
|
Aug 10 05:30:55 PM PDT 24 |
Aug 10 05:31:56 PM PDT 24 |
9419155818 ps |
| T795 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1652796359 |
|
|
Aug 10 05:31:31 PM PDT 24 |
Aug 10 05:32:45 PM PDT 24 |
2468895733 ps |
| T796 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.651157761 |
|
|
Aug 10 05:32:24 PM PDT 24 |
Aug 10 05:37:23 PM PDT 24 |
16593072089 ps |
| T797 |
/workspace/coverage/default/1.sram_ctrl_bijection.3525351520 |
|
|
Aug 10 05:30:14 PM PDT 24 |
Aug 10 06:04:41 PM PDT 24 |
87575413939 ps |
| T798 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3409565841 |
|
|
Aug 10 05:32:07 PM PDT 24 |
Aug 10 05:42:14 PM PDT 24 |
46715435638 ps |
| T799 |
/workspace/coverage/default/49.sram_ctrl_smoke.422190785 |
|
|
Aug 10 05:35:07 PM PDT 24 |
Aug 10 05:35:27 PM PDT 24 |
1738444767 ps |
| T800 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2546427395 |
|
|
Aug 10 05:31:27 PM PDT 24 |
Aug 10 05:36:33 PM PDT 24 |
4307960640 ps |
| T801 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1156868364 |
|
|
Aug 10 05:30:53 PM PDT 24 |
Aug 10 05:33:00 PM PDT 24 |
1671284936 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.937460306 |
|
|
Aug 10 05:33:01 PM PDT 24 |
Aug 10 05:33:33 PM PDT 24 |
742830770 ps |
| T803 |
/workspace/coverage/default/17.sram_ctrl_smoke.3558646745 |
|
|
Aug 10 05:30:55 PM PDT 24 |
Aug 10 05:31:20 PM PDT 24 |
2852014132 ps |
| T804 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3898709267 |
|
|
Aug 10 05:30:13 PM PDT 24 |
Aug 10 05:30:26 PM PDT 24 |
4643826496 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2856578874 |
|
|
Aug 10 05:30:52 PM PDT 24 |
Aug 10 05:35:45 PM PDT 24 |
4599966721 ps |
| T806 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3827852849 |
|
|
Aug 10 05:30:44 PM PDT 24 |
Aug 10 05:30:48 PM PDT 24 |
504015647 ps |
| T807 |
/workspace/coverage/default/40.sram_ctrl_executable.3208611985 |
|
|
Aug 10 05:33:35 PM PDT 24 |
Aug 10 05:55:54 PM PDT 24 |
136958972561 ps |
| T808 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.231218759 |
|
|
Aug 10 05:34:44 PM PDT 24 |
Aug 10 05:34:48 PM PDT 24 |
1248222952 ps |
| T809 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.684367401 |
|
|
Aug 10 05:31:02 PM PDT 24 |
Aug 10 05:31:10 PM PDT 24 |
693249342 ps |
| T810 |
/workspace/coverage/default/24.sram_ctrl_partial_access.66189768 |
|
|
Aug 10 05:31:36 PM PDT 24 |
Aug 10 05:31:55 PM PDT 24 |
2123412343 ps |
| T811 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2021996835 |
|
|
Aug 10 05:30:41 PM PDT 24 |
Aug 10 05:31:00 PM PDT 24 |
4196399365 ps |
| T812 |
/workspace/coverage/default/9.sram_ctrl_executable.314227479 |
|
|
Aug 10 05:30:33 PM PDT 24 |
Aug 10 05:43:54 PM PDT 24 |
47519850941 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1476404329 |
|
|
Aug 10 05:30:27 PM PDT 24 |
Aug 10 05:34:10 PM PDT 24 |
6520640693 ps |
| T814 |
/workspace/coverage/default/34.sram_ctrl_regwen.2630903600 |
|
|
Aug 10 05:32:43 PM PDT 24 |
Aug 10 05:44:07 PM PDT 24 |
7242510824 ps |
| T815 |
/workspace/coverage/default/35.sram_ctrl_partial_access.415500213 |
|
|
Aug 10 05:32:54 PM PDT 24 |
Aug 10 05:33:17 PM PDT 24 |
960703730 ps |
| T816 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1066398286 |
|
|
Aug 10 05:32:07 PM PDT 24 |
Aug 10 05:35:51 PM PDT 24 |
3896392557 ps |
| T817 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2632038645 |
|
|
Aug 10 05:34:27 PM PDT 24 |
Aug 10 05:34:28 PM PDT 24 |
45031367 ps |
| T818 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.946021591 |
|
|
Aug 10 05:33:43 PM PDT 24 |
Aug 10 05:34:08 PM PDT 24 |
2545235259 ps |
| T819 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2332371915 |
|
|
Aug 10 05:30:26 PM PDT 24 |
Aug 10 05:31:19 PM PDT 24 |
2500911029 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_bijection.3970537674 |
|
|
Aug 10 05:31:43 PM PDT 24 |
Aug 10 05:53:36 PM PDT 24 |
248237970575 ps |
| T821 |
/workspace/coverage/default/19.sram_ctrl_alert_test.4180794281 |
|
|
Aug 10 05:31:12 PM PDT 24 |
Aug 10 05:31:13 PM PDT 24 |
36667009 ps |
| T822 |
/workspace/coverage/default/44.sram_ctrl_regwen.3255028569 |
|
|
Aug 10 05:34:19 PM PDT 24 |
Aug 10 05:51:09 PM PDT 24 |
3331410900 ps |
| T823 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3838418539 |
|
|
Aug 10 05:30:36 PM PDT 24 |
Aug 10 05:35:36 PM PDT 24 |
5154972122 ps |
| T824 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.783423984 |
|
|
Aug 10 05:31:51 PM PDT 24 |
Aug 10 05:36:09 PM PDT 24 |
12394826039 ps |
| T825 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1268555340 |
|
|
Aug 10 05:31:03 PM PDT 24 |
Aug 10 05:33:43 PM PDT 24 |
20533951760 ps |
| T826 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1232271368 |
|
|
Aug 10 05:30:31 PM PDT 24 |
Aug 10 05:49:14 PM PDT 24 |
53274908348 ps |
| T827 |
/workspace/coverage/default/6.sram_ctrl_executable.3555658079 |
|
|
Aug 10 05:30:24 PM PDT 24 |
Aug 10 05:37:44 PM PDT 24 |
11444507883 ps |
| T828 |
/workspace/coverage/default/27.sram_ctrl_bijection.1363638917 |
|
|
Aug 10 05:31:52 PM PDT 24 |
Aug 10 05:55:48 PM PDT 24 |
124999406904 ps |
| T829 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1194319533 |
|
|
Aug 10 05:33:32 PM PDT 24 |
Aug 10 05:34:47 PM PDT 24 |
40388118577 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1354029784 |
|
|
Aug 10 05:32:53 PM PDT 24 |
Aug 10 07:09:37 PM PDT 24 |
268704224172 ps |
| T831 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2609886741 |
|
|
Aug 10 05:33:35 PM PDT 24 |
Aug 10 05:36:07 PM PDT 24 |
1377424335 ps |
| T832 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1072086304 |
|
|
Aug 10 05:31:51 PM PDT 24 |
Aug 10 05:31:54 PM PDT 24 |
351751729 ps |
| T833 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3193721411 |
|
|
Aug 10 05:30:19 PM PDT 24 |
Aug 10 05:33:16 PM PDT 24 |
4379300876 ps |
| T834 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3028525576 |
|
|
Aug 10 05:31:45 PM PDT 24 |
Aug 10 05:34:49 PM PDT 24 |
3644332999 ps |
| T835 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3937302662 |
|
|
Aug 10 05:31:51 PM PDT 24 |
Aug 10 05:32:00 PM PDT 24 |
2219447294 ps |
| T836 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2389725415 |
|
|
Aug 10 05:30:14 PM PDT 24 |
Aug 10 05:34:46 PM PDT 24 |
4067936874 ps |
| T837 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1362614961 |
|
|
Aug 10 05:33:51 PM PDT 24 |
Aug 10 05:40:39 PM PDT 24 |
116519955580 ps |
| T838 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.222230430 |
|
|
Aug 10 05:33:24 PM PDT 24 |
Aug 10 05:33:28 PM PDT 24 |
352571666 ps |
| T839 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1361711956 |
|
|
Aug 10 05:30:48 PM PDT 24 |
Aug 10 05:34:39 PM PDT 24 |
15253013745 ps |
| T840 |
/workspace/coverage/default/48.sram_ctrl_bijection.2750403138 |
|
|
Aug 10 05:34:58 PM PDT 24 |
Aug 10 05:44:19 PM PDT 24 |
35962028410 ps |
| T841 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.847920865 |
|
|
Aug 10 05:33:34 PM PDT 24 |
Aug 10 05:33:37 PM PDT 24 |
1355894076 ps |
| T842 |
/workspace/coverage/default/13.sram_ctrl_stress_all.3075688121 |
|
|
Aug 10 05:30:51 PM PDT 24 |
Aug 10 06:52:13 PM PDT 24 |
319809726376 ps |
| T843 |
/workspace/coverage/default/36.sram_ctrl_smoke.3501903899 |
|
|
Aug 10 05:32:53 PM PDT 24 |
Aug 10 05:34:17 PM PDT 24 |
3141060547 ps |
| T844 |
/workspace/coverage/default/15.sram_ctrl_partial_access.4141155706 |
|
|
Aug 10 05:30:51 PM PDT 24 |
Aug 10 05:31:12 PM PDT 24 |
2641822601 ps |
| T845 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.992494481 |
|
|
Aug 10 05:30:11 PM PDT 24 |
Aug 10 05:32:23 PM PDT 24 |
8584198280 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.255628542 |
|
|
Aug 10 05:32:52 PM PDT 24 |
Aug 10 05:39:11 PM PDT 24 |
82790388418 ps |
| T847 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3016829927 |
|
|
Aug 10 05:32:53 PM PDT 24 |
Aug 10 05:42:34 PM PDT 24 |
27704080124 ps |
| T848 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3866600789 |
|
|
Aug 10 05:31:04 PM PDT 24 |
Aug 10 05:52:41 PM PDT 24 |
58869892743 ps |
| T849 |
/workspace/coverage/default/33.sram_ctrl_regwen.1678173298 |
|
|
Aug 10 05:32:34 PM PDT 24 |
Aug 10 05:39:26 PM PDT 24 |
18288221401 ps |
| T850 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4156012298 |
|
|
Aug 10 05:30:27 PM PDT 24 |
Aug 10 05:30:30 PM PDT 24 |
365435648 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_regwen.1395693918 |
|
|
Aug 10 05:31:18 PM PDT 24 |
Aug 10 05:53:45 PM PDT 24 |
37484511367 ps |
| T852 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4083951510 |
|
|
Aug 10 05:30:25 PM PDT 24 |
Aug 10 05:36:12 PM PDT 24 |
28675683560 ps |
| T853 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2558434641 |
|
|
Aug 10 05:34:37 PM PDT 24 |
Aug 10 05:36:09 PM PDT 24 |
8528547992 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_alert_test.4143042410 |
|
|
Aug 10 05:30:45 PM PDT 24 |
Aug 10 05:30:46 PM PDT 24 |
31049357 ps |
| T855 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.956239734 |
|
|
Aug 10 05:30:11 PM PDT 24 |
Aug 10 05:40:31 PM PDT 24 |
23287719445 ps |
| T856 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1677800358 |
|
|
Aug 10 05:30:44 PM PDT 24 |
Aug 10 05:31:57 PM PDT 24 |
12625910811 ps |
| T857 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3628181811 |
|
|
Aug 10 05:30:25 PM PDT 24 |
Aug 10 05:31:49 PM PDT 24 |
12838270724 ps |
| T858 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2229081330 |
|
|
Aug 10 05:30:20 PM PDT 24 |
Aug 10 05:30:23 PM PDT 24 |
365408126 ps |
| T859 |
/workspace/coverage/default/16.sram_ctrl_bijection.2726567752 |
|
|
Aug 10 05:31:02 PM PDT 24 |
Aug 10 05:40:02 PM PDT 24 |
25579221553 ps |
| T860 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3104911222 |
|
|
Aug 10 05:34:11 PM PDT 24 |
Aug 10 05:35:43 PM PDT 24 |
2660648500 ps |
| T861 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3771966334 |
|
|
Aug 10 05:34:47 PM PDT 24 |
Aug 10 05:45:22 PM PDT 24 |
34813848708 ps |
| T862 |
/workspace/coverage/default/24.sram_ctrl_bijection.3490345976 |
|
|
Aug 10 05:31:34 PM PDT 24 |
Aug 10 05:59:08 PM PDT 24 |
90129612045 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3256296392 |
|
|
Aug 10 05:32:43 PM PDT 24 |
Aug 10 05:36:46 PM PDT 24 |
7948132199 ps |
| T864 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2235872250 |
|
|
Aug 10 05:30:22 PM PDT 24 |
Aug 10 05:34:48 PM PDT 24 |
8387822355 ps |
| T865 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2468605810 |
|
|
Aug 10 05:33:08 PM PDT 24 |
Aug 10 05:40:48 PM PDT 24 |
21282659634 ps |
| T866 |
/workspace/coverage/default/13.sram_ctrl_smoke.1917509844 |
|
|
Aug 10 05:30:43 PM PDT 24 |
Aug 10 05:31:19 PM PDT 24 |
1990783302 ps |
| T867 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3666015908 |
|
|
Aug 10 05:30:12 PM PDT 24 |
Aug 10 05:34:18 PM PDT 24 |
4036264630 ps |
| T868 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2450201591 |
|
|
Aug 10 05:32:59 PM PDT 24 |
Aug 10 05:33:07 PM PDT 24 |
239558714 ps |
| T869 |
/workspace/coverage/default/27.sram_ctrl_stress_all.415844295 |
|
|
Aug 10 05:31:58 PM PDT 24 |
Aug 10 06:19:12 PM PDT 24 |
34178521353 ps |
| T870 |
/workspace/coverage/default/14.sram_ctrl_regwen.3431484042 |
|
|
Aug 10 05:30:48 PM PDT 24 |
Aug 10 05:45:54 PM PDT 24 |
38147529555 ps |
| T871 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2559316018 |
|
|
Aug 10 05:30:37 PM PDT 24 |
Aug 10 05:31:31 PM PDT 24 |
7887082287 ps |
| T872 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.801429035 |
|
|
Aug 10 05:32:41 PM PDT 24 |
Aug 10 05:35:14 PM PDT 24 |
5000788751 ps |
| T873 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.522067758 |
|
|
Aug 10 05:34:28 PM PDT 24 |
Aug 10 05:37:08 PM PDT 24 |
28900282139 ps |
| T874 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3822273387 |
|
|
Aug 10 05:30:45 PM PDT 24 |
Aug 10 05:37:00 PM PDT 24 |
53535395753 ps |
| T875 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1467111430 |
|
|
Aug 10 05:33:30 PM PDT 24 |
Aug 10 05:33:41 PM PDT 24 |
1047723118 ps |
| T876 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.1019522609 |
|
|
Aug 10 05:30:33 PM PDT 24 |
Aug 10 05:32:52 PM PDT 24 |
763245486 ps |
| T877 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2082807622 |
|
|
Aug 10 05:31:35 PM PDT 24 |
Aug 10 05:33:34 PM PDT 24 |
1628897622 ps |
| T878 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1042991253 |
|
|
Aug 10 05:32:00 PM PDT 24 |
Aug 10 05:32:12 PM PDT 24 |
729939473 ps |
| T879 |
/workspace/coverage/default/9.sram_ctrl_bijection.2170611492 |
|
|
Aug 10 05:30:32 PM PDT 24 |
Aug 10 06:03:38 PM PDT 24 |
26574751624 ps |
| T880 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2182024158 |
|
|
Aug 10 05:32:32 PM PDT 24 |
Aug 10 05:35:11 PM PDT 24 |
4703702520 ps |
| T881 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2003839985 |
|
|
Aug 10 05:32:24 PM PDT 24 |
Aug 10 05:32:27 PM PDT 24 |
1352066564 ps |
| T882 |
/workspace/coverage/default/3.sram_ctrl_executable.4035136009 |
|
|
Aug 10 05:30:24 PM PDT 24 |
Aug 10 05:53:34 PM PDT 24 |
21317162555 ps |
| T883 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3426839669 |
|
|
Aug 10 05:34:21 PM PDT 24 |
Aug 10 05:45:24 PM PDT 24 |
7000880649 ps |
| T884 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1578133203 |
|
|
Aug 10 05:34:58 PM PDT 24 |
Aug 10 05:51:30 PM PDT 24 |
72018093962 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_regwen.1166831183 |
|
|
Aug 10 05:30:45 PM PDT 24 |
Aug 10 05:32:25 PM PDT 24 |
4416577522 ps |
| T886 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.664352382 |
|
|
Aug 10 05:32:09 PM PDT 24 |
Aug 10 05:32:12 PM PDT 24 |
2108927176 ps |
| T887 |
/workspace/coverage/default/49.sram_ctrl_executable.3534468078 |
|
|
Aug 10 05:35:07 PM PDT 24 |
Aug 10 05:49:12 PM PDT 24 |
39619969563 ps |
| T888 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3833276027 |
|
|
Aug 10 05:30:53 PM PDT 24 |
Aug 10 05:32:55 PM PDT 24 |
4301046920 ps |
| T889 |
/workspace/coverage/default/25.sram_ctrl_regwen.4147170324 |
|
|
Aug 10 05:31:40 PM PDT 24 |
Aug 10 05:37:52 PM PDT 24 |
3677644756 ps |
| T890 |
/workspace/coverage/default/19.sram_ctrl_regwen.3995818831 |
|
|
Aug 10 05:31:02 PM PDT 24 |
Aug 10 05:35:43 PM PDT 24 |
7584378679 ps |
| T891 |
/workspace/coverage/default/46.sram_ctrl_partial_access.672273105 |
|
|
Aug 10 05:34:30 PM PDT 24 |
Aug 10 05:34:53 PM PDT 24 |
1750849297 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1260646717 |
|
|
Aug 10 05:30:47 PM PDT 24 |
Aug 10 05:43:17 PM PDT 24 |
16861063841 ps |
| T893 |
/workspace/coverage/default/46.sram_ctrl_bijection.3696895900 |
|
|
Aug 10 05:34:31 PM PDT 24 |
Aug 10 06:02:07 PM PDT 24 |
72831555433 ps |
| T894 |
/workspace/coverage/default/12.sram_ctrl_bijection.3622540466 |
|
|
Aug 10 05:30:40 PM PDT 24 |
Aug 10 06:01:30 PM PDT 24 |
25273219687 ps |
| T895 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3544848791 |
|
|
Aug 10 05:30:43 PM PDT 24 |
Aug 10 05:32:01 PM PDT 24 |
1397249017 ps |
| T896 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2216635670 |
|
|
Aug 10 05:31:18 PM PDT 24 |
Aug 10 05:35:38 PM PDT 24 |
4066675110 ps |
| T897 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3823343535 |
|
|
Aug 10 05:30:26 PM PDT 24 |
Aug 10 05:32:30 PM PDT 24 |
3470409667 ps |
| T898 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.378394693 |
|
|
Aug 10 05:32:08 PM PDT 24 |
Aug 10 05:34:26 PM PDT 24 |
17453055801 ps |
| T899 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.373000082 |
|
|
Aug 10 05:32:42 PM PDT 24 |
Aug 10 05:38:46 PM PDT 24 |
24198902192 ps |
| T900 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3704415964 |
|
|
Aug 10 05:30:39 PM PDT 24 |
Aug 10 05:34:08 PM PDT 24 |
3315831919 ps |
| T901 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2115096875 |
|
|
Aug 10 05:30:51 PM PDT 24 |
Aug 10 06:22:43 PM PDT 24 |
20106874480 ps |
| T902 |
/workspace/coverage/default/39.sram_ctrl_stress_all.643655799 |
|
|
Aug 10 05:33:30 PM PDT 24 |
Aug 10 07:22:51 PM PDT 24 |
445891793852 ps |
| T903 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2811595753 |
|
|
Aug 10 05:34:37 PM PDT 24 |
Aug 10 06:26:25 PM PDT 24 |
53030439865 ps |
| T904 |
/workspace/coverage/default/26.sram_ctrl_smoke.821703668 |
|
|
Aug 10 05:31:42 PM PDT 24 |
Aug 10 05:31:48 PM PDT 24 |
627992651 ps |
| T905 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3709910028 |
|
|
Aug 10 05:31:16 PM PDT 24 |
Aug 10 05:33:11 PM PDT 24 |
2880498039 ps |
| T906 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2059839464 |
|
|
Aug 10 05:32:33 PM PDT 24 |
Aug 10 06:01:11 PM PDT 24 |
76156749091 ps |
| T907 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1253137326 |
|
|
Aug 10 05:30:52 PM PDT 24 |
Aug 10 05:36:36 PM PDT 24 |
5526591346 ps |
| T908 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2659039417 |
|
|
Aug 10 05:32:08 PM PDT 24 |
Aug 10 05:52:47 PM PDT 24 |
48015861401 ps |
| T909 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.299109177 |
|
|
Aug 10 05:30:13 PM PDT 24 |
Aug 10 05:33:03 PM PDT 24 |
5638338623 ps |
| T910 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3066272392 |
|
|
Aug 10 05:30:14 PM PDT 24 |
Aug 10 05:31:38 PM PDT 24 |
2617529822 ps |
| T911 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3688397433 |
|
|
Aug 10 05:30:27 PM PDT 24 |
Aug 10 05:33:42 PM PDT 24 |
2731130769 ps |
| T912 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2883069767 |
|
|
Aug 10 05:30:57 PM PDT 24 |
Aug 10 05:31:30 PM PDT 24 |
2997788196 ps |
| T913 |
/workspace/coverage/default/2.sram_ctrl_stress_all.4081452345 |
|
|
Aug 10 05:30:27 PM PDT 24 |
Aug 10 06:51:50 PM PDT 24 |
743625147953 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4056056671 |
|
|
Aug 10 05:34:57 PM PDT 24 |
Aug 10 05:35:00 PM PDT 24 |
349541951 ps |
| T915 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.229091908 |
|
|
Aug 10 05:33:24 PM PDT 24 |
Aug 10 05:45:00 PM PDT 24 |
12324320067 ps |
| T916 |
/workspace/coverage/default/20.sram_ctrl_alert_test.827588972 |
|
|
Aug 10 05:31:12 PM PDT 24 |
Aug 10 05:31:12 PM PDT 24 |
46240055 ps |
| T917 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3143964695 |
|
|
Aug 10 05:34:57 PM PDT 24 |
Aug 10 06:02:43 PM PDT 24 |
22338748382 ps |
| T918 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.103769860 |
|
|
Aug 10 05:30:16 PM PDT 24 |
Aug 10 05:30:36 PM PDT 24 |
746901898 ps |
| T919 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1847235194 |
|
|
Aug 10 05:33:08 PM PDT 24 |
Aug 10 05:48:57 PM PDT 24 |
16551370023 ps |
| T920 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.428095089 |
|
|
Aug 10 05:31:42 PM PDT 24 |
Aug 10 05:31:49 PM PDT 24 |
1091409264 ps |
| T921 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1152362905 |
|
|
Aug 10 05:33:09 PM PDT 24 |
Aug 10 05:41:26 PM PDT 24 |
97454208519 ps |
| T922 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.127027072 |
|
|
Aug 10 05:31:42 PM PDT 24 |
Aug 10 05:31:46 PM PDT 24 |
369072971 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1145078609 |
|
|
Aug 10 05:31:36 PM PDT 24 |
Aug 10 05:35:19 PM PDT 24 |
6225961157 ps |
| T924 |
/workspace/coverage/default/15.sram_ctrl_stress_all.1353858340 |
|
|
Aug 10 05:30:50 PM PDT 24 |
Aug 10 06:52:30 PM PDT 24 |
143878876887 ps |
| T925 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1588416282 |
|
|
Aug 10 05:31:21 PM PDT 24 |
Aug 10 05:32:46 PM PDT 24 |
5395781601 ps |
| T926 |
/workspace/coverage/default/2.sram_ctrl_bijection.3070787502 |
|
|
Aug 10 05:30:15 PM PDT 24 |
Aug 10 06:17:15 PM PDT 24 |
920531051164 ps |
| T927 |
/workspace/coverage/default/8.sram_ctrl_smoke.447442630 |
|
|
Aug 10 05:30:30 PM PDT 24 |
Aug 10 05:30:51 PM PDT 24 |
3361320870 ps |
| T928 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3231206559 |
|
|
Aug 10 05:30:32 PM PDT 24 |
Aug 10 05:31:08 PM PDT 24 |
6208094193 ps |
| T929 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1350311836 |
|
|
Aug 10 05:30:26 PM PDT 24 |
Aug 10 06:13:36 PM PDT 24 |
261209038154 ps |
| T930 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2880841471 |
|
|
Aug 10 05:30:56 PM PDT 24 |
Aug 10 05:30:59 PM PDT 24 |
352581541 ps |
| T931 |
/workspace/coverage/default/35.sram_ctrl_smoke.3690639746 |
|
|
Aug 10 05:32:42 PM PDT 24 |
Aug 10 05:32:49 PM PDT 24 |
1673721898 ps |
| T932 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3069316459 |
|
|
Aug 10 05:31:01 PM PDT 24 |
Aug 10 05:36:30 PM PDT 24 |
11226538486 ps |
| T933 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.836513353 |
|
|
Aug 10 05:30:29 PM PDT 24 |
Aug 10 05:31:12 PM PDT 24 |
758471599 ps |
| T934 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.346655436 |
|
|
Aug 10 05:34:09 PM PDT 24 |
Aug 10 05:34:13 PM PDT 24 |
1411930853 ps |
| T935 |
/workspace/coverage/default/9.sram_ctrl_regwen.3621400733 |
|
|
Aug 10 05:30:42 PM PDT 24 |
Aug 10 05:34:11 PM PDT 24 |
2777949755 ps |
| T936 |
/workspace/coverage/default/42.sram_ctrl_stress_all.2481673450 |
|
|
Aug 10 05:34:01 PM PDT 24 |
Aug 10 07:28:31 PM PDT 24 |
152753878859 ps |
| T937 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2908753008 |
|
|
Aug 10 05:30:42 PM PDT 24 |
Aug 10 05:32:28 PM PDT 24 |
3171417257 ps |
| T938 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1260018628 |
|
|
Aug 10 05:31:17 PM PDT 24 |
Aug 10 05:31:18 PM PDT 24 |
36207351 ps |
| T939 |
/workspace/coverage/default/32.sram_ctrl_alert_test.213109120 |
|
|
Aug 10 05:32:32 PM PDT 24 |
Aug 10 05:32:33 PM PDT 24 |
18598624 ps |
| T940 |
/workspace/coverage/default/11.sram_ctrl_partial_access.767880615 |
|
|
Aug 10 05:30:34 PM PDT 24 |
Aug 10 05:30:53 PM PDT 24 |
2488221206 ps |
| T941 |
/workspace/coverage/default/6.sram_ctrl_alert_test.324095712 |
|
|
Aug 10 05:30:28 PM PDT 24 |
Aug 10 05:30:29 PM PDT 24 |
43734236 ps |
| T942 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.350802853 |
|
|
Aug 10 05:32:24 PM PDT 24 |
Aug 10 05:37:12 PM PDT 24 |
2990003919 ps |
| T66 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.880628429 |
|
|
Aug 10 05:23:51 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
52091238 ps |
| T943 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1532562427 |
|
|
Aug 10 05:24:11 PM PDT 24 |
Aug 10 05:24:15 PM PDT 24 |
348130047 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3727533853 |
|
|
Aug 10 05:23:44 PM PDT 24 |
Aug 10 05:24:33 PM PDT 24 |
7553486126 ps |
| T944 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4117987537 |
|
|
Aug 10 05:24:08 PM PDT 24 |
Aug 10 05:24:13 PM PDT 24 |
2152520794 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3433095663 |
|
|
Aug 10 05:23:59 PM PDT 24 |
Aug 10 05:24:00 PM PDT 24 |
21134609 ps |
| T945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4109871495 |
|
|
Aug 10 05:23:51 PM PDT 24 |
Aug 10 05:23:53 PM PDT 24 |
278958472 ps |
| T76 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1572382157 |
|
|
Aug 10 05:23:53 PM PDT 24 |
Aug 10 05:24:43 PM PDT 24 |
7376953272 ps |
| T77 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2780489757 |
|
|
Aug 10 05:23:50 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
27790348 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2302536591 |
|
|
Aug 10 05:23:45 PM PDT 24 |
Aug 10 05:23:45 PM PDT 24 |
14289243 ps |
| T100 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3324873322 |
|
|
Aug 10 05:24:06 PM PDT 24 |
Aug 10 05:24:08 PM PDT 24 |
50903147 ps |
| T62 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2575345920 |
|
|
Aug 10 05:23:58 PM PDT 24 |
Aug 10 05:24:00 PM PDT 24 |
177334972 ps |
| T109 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1996429173 |
|
|
Aug 10 05:24:06 PM PDT 24 |
Aug 10 05:24:07 PM PDT 24 |
15521554 ps |
| T947 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1194514740 |
|
|
Aug 10 05:24:04 PM PDT 24 |
Aug 10 05:24:13 PM PDT 24 |
71793575 ps |
| T63 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.546679645 |
|
|
Aug 10 05:23:44 PM PDT 24 |
Aug 10 05:23:46 PM PDT 24 |
321914124 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1535576739 |
|
|
Aug 10 05:24:05 PM PDT 24 |
Aug 10 05:24:09 PM PDT 24 |
1395828377 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.91007672 |
|
|
Aug 10 05:23:45 PM PDT 24 |
Aug 10 05:23:46 PM PDT 24 |
67800262 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.929362640 |
|
|
Aug 10 05:23:44 PM PDT 24 |
Aug 10 05:23:47 PM PDT 24 |
237045261 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2395467581 |
|
|
Aug 10 05:24:05 PM PDT 24 |
Aug 10 05:24:09 PM PDT 24 |
360898460 ps |
| T79 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2355319503 |
|
|
Aug 10 05:24:12 PM PDT 24 |
Aug 10 05:24:13 PM PDT 24 |
44932328 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2195181716 |
|
|
Aug 10 05:23:46 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
3806195561 ps |
| T80 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1824665755 |
|
|
Aug 10 05:23:53 PM PDT 24 |
Aug 10 05:24:47 PM PDT 24 |
37091803427 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2132657287 |
|
|
Aug 10 05:23:47 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
163136331 ps |
| T125 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3515106361 |
|
|
Aug 10 05:23:47 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
577698184 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1240826063 |
|
|
Aug 10 05:24:03 PM PDT 24 |
Aug 10 05:24:04 PM PDT 24 |
74367202 ps |
| T952 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2493859982 |
|
|
Aug 10 05:24:13 PM PDT 24 |
Aug 10 05:24:17 PM PDT 24 |
364376983 ps |
| T81 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.908656972 |
|
|
Aug 10 05:24:14 PM PDT 24 |
Aug 10 05:24:14 PM PDT 24 |
38707628 ps |
| T101 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.371860041 |
|
|
Aug 10 05:24:11 PM PDT 24 |
Aug 10 05:24:39 PM PDT 24 |
15466839511 ps |
| T131 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.213002696 |
|
|
Aug 10 05:24:00 PM PDT 24 |
Aug 10 05:24:03 PM PDT 24 |
270483861 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.733378155 |
|
|
Aug 10 05:24:07 PM PDT 24 |
Aug 10 05:24:08 PM PDT 24 |
44628498 ps |
| T103 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2401637826 |
|
|
Aug 10 05:23:56 PM PDT 24 |
Aug 10 05:23:57 PM PDT 24 |
20970791 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3320379802 |
|
|
Aug 10 05:24:04 PM PDT 24 |
Aug 10 05:24:05 PM PDT 24 |
35279087 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2749854538 |
|
|
Aug 10 05:24:01 PM PDT 24 |
Aug 10 05:24:01 PM PDT 24 |
37671005 ps |
| T955 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4043668721 |
|
|
Aug 10 05:23:51 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
14183295 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3162848308 |
|
|
Aug 10 05:23:45 PM PDT 24 |
Aug 10 05:23:46 PM PDT 24 |
84111485 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1253737789 |
|
|
Aug 10 05:23:43 PM PDT 24 |
Aug 10 05:24:35 PM PDT 24 |
7569066829 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1585633361 |
|
|
Aug 10 05:24:19 PM PDT 24 |
Aug 10 05:24:23 PM PDT 24 |
591364133 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4052660422 |
|
|
Aug 10 05:23:48 PM PDT 24 |
Aug 10 05:23:48 PM PDT 24 |
124806362 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4091997561 |
|
|
Aug 10 05:24:03 PM PDT 24 |
Aug 10 05:24:55 PM PDT 24 |
8142971599 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1954562925 |
|
|
Aug 10 05:24:15 PM PDT 24 |
Aug 10 05:24:16 PM PDT 24 |
185954259 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2114742227 |
|
|
Aug 10 05:24:07 PM PDT 24 |
Aug 10 05:24:08 PM PDT 24 |
91580279 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.833210982 |
|
|
Aug 10 05:23:48 PM PDT 24 |
Aug 10 05:23:49 PM PDT 24 |
13724351 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1025435447 |
|
|
Aug 10 05:24:08 PM PDT 24 |
Aug 10 05:24:36 PM PDT 24 |
10578435149 ps |
| T960 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1815547165 |
|
|
Aug 10 05:23:52 PM PDT 24 |
Aug 10 05:23:56 PM PDT 24 |
364274631 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.231530978 |
|
|
Aug 10 05:23:47 PM PDT 24 |
Aug 10 05:23:51 PM PDT 24 |
1432767221 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1886423652 |
|
|
Aug 10 05:23:50 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
146244964 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3223728141 |
|
|
Aug 10 05:23:56 PM PDT 24 |
Aug 10 05:23:57 PM PDT 24 |
22265172 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.583836315 |
|
|
Aug 10 05:23:46 PM PDT 24 |
Aug 10 05:23:46 PM PDT 24 |
145476335 ps |
| T965 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3900709058 |
|
|
Aug 10 05:23:45 PM PDT 24 |
Aug 10 05:23:45 PM PDT 24 |
28443778 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.627158245 |
|
|
Aug 10 05:23:52 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
101720628 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2819438666 |
|
|
Aug 10 05:23:50 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
31694336 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4115639266 |
|
|
Aug 10 05:23:44 PM PDT 24 |
Aug 10 05:23:45 PM PDT 24 |
16084918 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1021992184 |
|
|
Aug 10 05:24:01 PM PDT 24 |
Aug 10 05:24:06 PM PDT 24 |
133280263 ps |
| T970 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1052168164 |
|
|
Aug 10 05:24:14 PM PDT 24 |
Aug 10 05:24:18 PM PDT 24 |
691774262 ps |
| T129 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3310955420 |
|
|
Aug 10 05:24:07 PM PDT 24 |
Aug 10 05:24:09 PM PDT 24 |
556503048 ps |
| T971 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2529144899 |
|
|
Aug 10 05:23:45 PM PDT 24 |
Aug 10 05:24:47 PM PDT 24 |
25152200206 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1465626362 |
|
|
Aug 10 05:23:52 PM PDT 24 |
Aug 10 05:23:54 PM PDT 24 |
44926930 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1999086079 |
|
|
Aug 10 05:23:53 PM PDT 24 |
Aug 10 05:23:54 PM PDT 24 |
248434108 ps |
| T974 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2672936992 |
|
|
Aug 10 05:24:12 PM PDT 24 |
Aug 10 05:24:13 PM PDT 24 |
61555083 ps |
| T130 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2626620413 |
|
|
Aug 10 05:23:50 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
171560112 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4021305169 |
|
|
Aug 10 05:23:52 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
24101624 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1859122245 |
|
|
Aug 10 05:23:44 PM PDT 24 |
Aug 10 05:23:44 PM PDT 24 |
67939161 ps |
| T975 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3760796015 |
|
|
Aug 10 05:23:59 PM PDT 24 |
Aug 10 05:24:01 PM PDT 24 |
78387658 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.626308880 |
|
|
Aug 10 05:24:19 PM PDT 24 |
Aug 10 05:25:16 PM PDT 24 |
7283496075 ps |
| T95 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.336547924 |
|
|
Aug 10 05:23:50 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
26590871 ps |
| T976 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2480367565 |
|
|
Aug 10 05:23:54 PM PDT 24 |
Aug 10 05:23:58 PM PDT 24 |
1397637888 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2756747316 |
|
|
Aug 10 05:23:51 PM PDT 24 |
Aug 10 05:23:51 PM PDT 24 |
17560232 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2233589202 |
|
|
Aug 10 05:23:56 PM PDT 24 |
Aug 10 05:23:57 PM PDT 24 |
41630192 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.353106525 |
|
|
Aug 10 05:24:05 PM PDT 24 |
Aug 10 05:24:07 PM PDT 24 |
325954151 ps |
| T134 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1544002376 |
|
|
Aug 10 05:24:07 PM PDT 24 |
Aug 10 05:24:08 PM PDT 24 |
157029328 ps |
| T96 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3011209000 |
|
|
Aug 10 05:23:46 PM PDT 24 |
Aug 10 05:23:47 PM PDT 24 |
18081013 ps |
| T980 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3603779022 |
|
|
Aug 10 05:23:48 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
523348390 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.763702557 |
|
|
Aug 10 05:23:42 PM PDT 24 |
Aug 10 05:23:46 PM PDT 24 |
138445056 ps |
| T982 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2542833701 |
|
|
Aug 10 05:23:47 PM PDT 24 |
Aug 10 05:23:52 PM PDT 24 |
153915717 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2061306880 |
|
|
Aug 10 05:24:09 PM PDT 24 |
Aug 10 05:24:17 PM PDT 24 |
73435827 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.166660089 |
|
|
Aug 10 05:23:57 PM PDT 24 |
Aug 10 05:24:01 PM PDT 24 |
363828859 ps |
| T985 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4158483191 |
|
|
Aug 10 05:23:46 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
47608983 ps |
| T986 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1412134625 |
|
|
Aug 10 05:23:49 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
38758263 ps |
| T132 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2983657837 |
|
|
Aug 10 05:24:03 PM PDT 24 |
Aug 10 05:24:05 PM PDT 24 |
1187511609 ps |
| T97 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3802715576 |
|
|
Aug 10 05:24:06 PM PDT 24 |
Aug 10 05:24:07 PM PDT 24 |
11614473 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3767540284 |
|
|
Aug 10 05:23:46 PM PDT 24 |
Aug 10 05:24:41 PM PDT 24 |
14419006819 ps |
| T987 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3491843668 |
|
|
Aug 10 05:23:56 PM PDT 24 |
Aug 10 05:23:57 PM PDT 24 |
17433791 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3645249464 |
|
|
Aug 10 05:23:42 PM PDT 24 |
Aug 10 05:23:42 PM PDT 24 |
39240702 ps |
| T99 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1120053622 |
|
|
Aug 10 05:24:11 PM PDT 24 |
Aug 10 05:24:44 PM PDT 24 |
15410339086 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.550798979 |
|
|
Aug 10 05:23:43 PM PDT 24 |
Aug 10 05:23:49 PM PDT 24 |
153753384 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2698978512 |
|
|
Aug 10 05:23:48 PM PDT 24 |
Aug 10 05:24:15 PM PDT 24 |
16774278027 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3018707991 |
|
|
Aug 10 05:24:13 PM PDT 24 |
Aug 10 05:24:15 PM PDT 24 |
74373103 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3129065365 |
|
|
Aug 10 05:23:47 PM PDT 24 |
Aug 10 05:24:18 PM PDT 24 |
16023313632 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3296162826 |
|
|
Aug 10 05:23:52 PM PDT 24 |
Aug 10 05:23:54 PM PDT 24 |
441214685 ps |
| T994 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1530096162 |
|
|
Aug 10 05:23:57 PM PDT 24 |
Aug 10 05:23:58 PM PDT 24 |
41290215 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1048540538 |
|
|
Aug 10 05:23:47 PM PDT 24 |
Aug 10 05:23:50 PM PDT 24 |
159138677 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1200668700 |
|
|
Aug 10 05:24:09 PM PDT 24 |
Aug 10 05:24:10 PM PDT 24 |
21909600 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3427859424 |
|
|
Aug 10 05:23:45 PM PDT 24 |
Aug 10 05:23:48 PM PDT 24 |
440282138 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2900826038 |
|
|
Aug 10 05:24:04 PM PDT 24 |
Aug 10 05:24:07 PM PDT 24 |
49826526 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2625565916 |
|
|
Aug 10 05:24:06 PM PDT 24 |
Aug 10 05:24:10 PM PDT 24 |
720494534 ps |
| T127 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.130473340 |
|
|
Aug 10 05:24:07 PM PDT 24 |
Aug 10 05:24:09 PM PDT 24 |
310345306 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2713520835 |
|
|
Aug 10 05:23:58 PM PDT 24 |
Aug 10 05:24:02 PM PDT 24 |
659111105 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3974012006 |
|
|
Aug 10 05:23:42 PM PDT 24 |
Aug 10 05:23:44 PM PDT 24 |
418333970 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2310849545 |
|
|
Aug 10 05:24:13 PM PDT 24 |
Aug 10 05:24:14 PM PDT 24 |
280125362 ps |