Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16454466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

147929977

1

T1

193822

T2

5403

T3

10000

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80939833	1			T1	974381		T2	3016		T3	4983
values[0x0]	40085664	1			T1	484979		T2	1410		T3	2559
values[0x1]	43358946	1			T1	489214		T2	1524		T3	2458

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8373678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156010765

1

T1

194349

T2

5690

T3

10000

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	544753	1			T1	7750		T2	40		T3	23
valid_sources[0x01]	562439	1			T1	7519		T2	35		T3	29
valid_sources[0x02]	520968	1			T1	7871		T2	17		T3	45
valid_sources[0x03]	572368	1			T1	7864		T2	27		T3	35
valid_sources[0x04]	560716	1			T1	7766		T2	28		T3	30
valid_sources[0x05]	519478	1			T1	7464		T2	12		T3	29
valid_sources[0x06]	556218	1			T1	7887		T2	24		T3	38
valid_sources[0x07]	576610	1			T1	7418		T2	22		T3	28
valid_sources[0x08]	514915	1			T1	7862		T2	25		T3	39
valid_sources[0x09]	574311	1			T1	7385		T2	31		T3	39
valid_sources[0x0a]	522934	1			T1	7254		T2	21		T3	43
valid_sources[0x0b]	554394	1			T1	7511		T2	27		T3	42
valid_sources[0x0c]	566229	1			T1	7662		T2	32		T3	44
valid_sources[0x0d]	563329	1			T1	7834		T2	13		T3	37
valid_sources[0x0e]	537858	1			T1	7639		T2	25		T3	53
valid_sources[0x0f]	591725	1			T1	7353		T2	36		T3	37
valid_sources[0x10]	581655	1			T1	7740		T2	24		T3	31
valid_sources[0x11]	526668	1			T1	7898		T2	23		T3	39
valid_sources[0x12]	515923	1			T1	7504		T2	16		T3	34
valid_sources[0x13]	527655	1			T1	7746		T2	33		T3	33
valid_sources[0x14]	537146	1			T1	7922		T2	34		T3	43
valid_sources[0x15]	530302	1			T1	7763		T2	21		T3	49
valid_sources[0x16]	538706	1			T1	7818		T2	31		T3	36
valid_sources[0x17]	538379	1			T1	7327		T2	35		T3	50
valid_sources[0x18]	512183	1			T1	7566		T2	15		T3	30
valid_sources[0x19]	587643	1			T1	7635		T2	34		T3	44
valid_sources[0x1a]	530390	1			T1	7472		T2	21		T3	59
valid_sources[0x1b]	567580	1			T1	7694		T2	24		T3	49
valid_sources[0x1c]	607442	1			T1	8064		T2	12		T3	35
valid_sources[0x1d]	531491	1			T1	7468		T2	40		T3	42
valid_sources[0x1e]	541526	1			T1	7491		T2	26		T3	27
valid_sources[0x1f]	529413	1			T1	7239		T2	33		T3	39
valid_sources[0x20]	519493	1			T1	7531		T2	29		T3	38
valid_sources[0x21]	575186	1			T1	7428		T2	23		T3	31
valid_sources[0x22]	566849	1			T1	7553		T2	28		T3	36
valid_sources[0x23]	574876	1			T1	7313		T2	21		T3	46
valid_sources[0x24]	524687	1			T1	7512		T2	30		T3	42
valid_sources[0x25]	522422	1			T1	7449		T2	53		T3	51
valid_sources[0x26]	572046	1			T1	7515		T2	14		T3	34
valid_sources[0x27]	538076	1			T1	7693		T2	15		T3	28
valid_sources[0x28]	636053	1			T1	7744		T2	14		T3	43
valid_sources[0x29]	666878	1			T1	7692		T2	27		T3	44
valid_sources[0x2a]	520453	1			T1	7334		T2	16		T3	43
valid_sources[0x2b]	1039693	1			T1	7464		T2	39		T3	43
valid_sources[0x2c]	758504	1			T1	7652		T2	39		T3	38
valid_sources[0x2d]	585696	1			T1	7721		T2	23		T3	35
valid_sources[0x2e]	553576	1			T1	7646		T2	9		T3	36
valid_sources[0x2f]	589297	1			T1	7927		T2	29		T3	35
valid_sources[0x30]	567444	1			T1	7835		T2	22		T3	38
valid_sources[0x31]	526950	1			T1	7809		T2	19		T3	42
valid_sources[0x32]	549195	1			T1	7697		T2	35		T3	39
valid_sources[0x33]	533238	1			T1	7588		T2	22		T3	36
valid_sources[0x34]	542822	1			T1	7597		T2	16		T3	32
valid_sources[0x35]	530946	1			T1	7701		T2	27		T3	46
valid_sources[0x36]	560881	1			T1	7304		T2	31		T3	28
valid_sources[0x37]	550703	1			T1	8076		T2	15		T3	52
valid_sources[0x38]	516211	1			T1	7816		T2	33		T3	33
valid_sources[0x39]	560424	1			T1	7406		T2	18		T3	41
valid_sources[0x3a]	573204	1			T1	7553		T2	29		T3	29
valid_sources[0x3b]	544346	1			T1	7733		T2	33		T3	37
valid_sources[0x3c]	558059	1			T1	7343		T2	13		T3	36
valid_sources[0x3d]	1969055	1			T1	7506		T2	16		T3	41
valid_sources[0x3e]	519197	1			T1	7722		T2	15		T3	46
valid_sources[0x3f]	623510	1			T1	7568		T2	28		T3	47
valid_sources[0x40]	1974340	1			T1	7210		T2	24		T3	27
valid_sources[0x41]	541733	1			T1	7733		T2	15		T3	44
valid_sources[0x42]	550215	1			T1	7292		T2	38		T3	63
valid_sources[0x43]	1430143	1			T1	7603		T2	32		T3	35
valid_sources[0x44]	587238	1			T1	7513		T2	34		T3	42
valid_sources[0x45]	555894	1			T1	7471		T2	24		T3	37
valid_sources[0x46]	517004	1			T1	7691		T2	31		T3	50
valid_sources[0x47]	516257	1			T1	7433		T2	31		T3	30
valid_sources[0x48]	526718	1			T1	7633		T2	10		T3	41
valid_sources[0x49]	573345	1			T1	7966		T2	21		T3	38
valid_sources[0x4a]	590015	1			T1	7679		T2	8		T3	38
valid_sources[0x4b]	563113	1			T1	7579		T2	18		T3	37
valid_sources[0x4c]	527084	1			T1	7656		T2	28		T3	34
valid_sources[0x4d]	527696	1			T1	7588		T2	20		T3	48
valid_sources[0x4e]	525223	1			T1	8078		T2	22		T3	36
valid_sources[0x4f]	573243	1			T1	7661		T2	20		T3	39
valid_sources[0x50]	523297	1			T1	7704		T2	30		T3	44
valid_sources[0x51]	537318	1			T1	7500		T2	14		T3	36
valid_sources[0x52]	570026	1			T1	7711		T2	34		T3	43
valid_sources[0x53]	584938	1			T1	7107		T2	31		T3	37
valid_sources[0x54]	562710	1			T1	7449		T2	21		T3	35
valid_sources[0x55]	550566	1			T1	7622		T2	19		T3	60
valid_sources[0x56]	545481	1			T1	7510		T2	29		T3	47
valid_sources[0x57]	550205	1			T1	7705		T2	46		T3	30
valid_sources[0x58]	540856	1			T1	7488		T2	46		T3	39
valid_sources[0x59]	644296	1			T1	7749		T2	31		T3	28
valid_sources[0x5a]	523076	1			T1	7502		T2	25		T3	50
valid_sources[0x5b]	529106	1			T1	7975		T2	22		T3	33
valid_sources[0x5c]	517073	1			T1	7604		T2	25		T3	46
valid_sources[0x5d]	549899	1			T1	7319		T2	14		T3	40
valid_sources[0x5e]	543905	1			T1	8035		T2	32		T3	41
valid_sources[0x5f]	570128	1			T1	7620		T2	25		T3	32
valid_sources[0x60]	532916	1			T1	7782		T2	16		T3	42
valid_sources[0x61]	530198	1			T1	7442		T2	6		T3	44
valid_sources[0x62]	525229	1			T1	7593		T2	18		T3	35
valid_sources[0x63]	707672	1			T1	7546		T2	13		T3	53
valid_sources[0x64]	601507	1			T1	7696		T2	19		T3	40
valid_sources[0x65]	605283	1			T1	7444		T2	12		T3	30
valid_sources[0x66]	513287	1			T1	7718		T2	14		T3	43
valid_sources[0x67]	571224	1			T1	7546		T2	15		T3	42
valid_sources[0x68]	554596	1			T1	7338		T2	25		T3	37
valid_sources[0x69]	589369	1			T1	7565		T2	20		T3	48
valid_sources[0x6a]	1152245	1			T1	7189		T2	23		T3	42
valid_sources[0x6b]	1050635	1			T1	7650		T2	21		T3	43
valid_sources[0x6c]	524503	1			T1	7653		T2	33		T3	42
valid_sources[0x6d]	542574	1			T1	7631		T2	9		T3	33
valid_sources[0x6e]	539486	1			T1	7353		T2	12		T3	36
valid_sources[0x6f]	1481981	1			T1	7726		T2	13		T3	39
valid_sources[0x70]	574061	1			T1	7470		T2	20		T3	37
valid_sources[0x71]	520971	1			T1	7802		T2	18		T3	44
valid_sources[0x72]	555821	1			T1	7618		T2	28		T3	44
valid_sources[0x73]	553557	1			T1	7554		T2	39		T3	43
valid_sources[0x74]	584412	1			T1	7774		T2	7		T3	47
valid_sources[0x75]	539447	1			T1	7581		T2	32		T3	50
valid_sources[0x76]	527360	1			T1	7495		T2	23		T3	39
valid_sources[0x77]	580428	1			T1	7675		T2	23		T3	42
valid_sources[0x78]	546212	1			T1	7543		T2	19		T3	42
valid_sources[0x79]	560532	1			T1	7657		T2	21		T3	36
valid_sources[0x7a]	518132	1			T1	7645		T2	15		T3	26
valid_sources[0x7b]	568994	1			T1	7593		T2	25		T3	49
valid_sources[0x7c]	553379	1			T1	7870		T2	22		T3	26
valid_sources[0x7d]	554823	1			T1	7761		T2	17		T3	39
valid_sources[0x7e]	531773	1			T1	7706		T2	20		T3	26
valid_sources[0x7f]	1821416	1			T1	7348		T2	27		T3	32
valid_sources[0x80]	562471	1			T1	7538		T2	33		T3	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72669535

1

T1

969189

T2

2728

T3

4983

values[0x0]

all_enables

biggest_size

37629061

1

T1

483423

T2

1337

T3

2559

values[0x1]

all_enables

biggest_size

37631381

1

T1

485608

T2

1338

T3

2458

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165550

1

T1

6

T3

1

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58107	1			T4	40		T5	30		T9	10
values[0x0]	73209	1			T1	20		T3	1		T8	2
values[0x1]	78820	1			T1	12		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

175934

1

T1

9

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	912	1			T13	1		T25	5		T141	2
valid_sources[0x01]	812	1			T25	33		T19	132		T35	1
valid_sources[0x02]	1218	1			T69	1		T6	2		T25	55
valid_sources[0x03]	592	1			T24	19		T15	1		T26	8
valid_sources[0x04]	719	1			T25	2		T26	1		T48	26
valid_sources[0x05]	706	1			T51	1		T48	19		T49	3
valid_sources[0x06]	796	1			T6	2		T39	4		T147	2
valid_sources[0x07]	573	1			T27	1		T35	1		T26	4
valid_sources[0x08]	628	1			T25	1		T26	3		T48	24
valid_sources[0x09]	691	1			T26	1		T48	18		T148	1
valid_sources[0x0a]	1143	1			T69	1		T147	1		T149	1
valid_sources[0x0b]	535	1			T69	1		T25	1		T51	1
valid_sources[0x0c]	973	1			T4	1		T24	1		T26	7
valid_sources[0x0d]	886	1			T23	1		T71	2		T6	1
valid_sources[0x0e]	978	1			T51	1		T48	33		T20	3
valid_sources[0x0f]	709	1			T6	1		T25	3		T48	22
valid_sources[0x10]	562	1			T25	4		T35	1		T48	16
valid_sources[0x11]	887	1			T69	1		T6	1		T39	3
valid_sources[0x12]	562	1			T6	1		T26	5		T48	27
valid_sources[0x13]	897	1			T25	1		T39	2		T141	1
valid_sources[0x14]	653	1			T4	1		T25	1		T26	1
valid_sources[0x15]	963	1			T6	1		T25	2		T35	1
valid_sources[0x16]	768	1			T25	1		T51	1		T15	1
valid_sources[0x17]	936	1			T6	1		T25	170		T53	1
valid_sources[0x18]	669	1			T25	1		T48	27		T66	7
valid_sources[0x19]	965	1			T65	1		T36	37		T48	23
valid_sources[0x1a]	1094	1			T27	1		T69	1		T48	16
valid_sources[0x1b]	851	1			T4	1		T25	1		T35	1
valid_sources[0x1c]	631	1			T12	1		T6	1		T15	1
valid_sources[0x1d]	677	1			T6	3		T35	1		T48	21
valid_sources[0x1e]	687	1			T25	4		T26	2		T48	24
valid_sources[0x1f]	646	1			T26	5		T48	25		T49	1
valid_sources[0x20]	856	1			T25	101		T26	3		T147	1
valid_sources[0x21]	1043	1			T6	2		T25	123		T51	1
valid_sources[0x22]	644	1			T27	1		T69	1		T39	1
valid_sources[0x23]	637	1			T27	1		T6	1		T51	1
valid_sources[0x24]	955	1			T5	25		T27	2		T48	26
valid_sources[0x25]	991	1			T48	19		T49	2		T50	6
valid_sources[0x26]	664	1			T5	6		T33	1		T6	1
valid_sources[0x27]	832	1			T27	1		T69	1		T35	1
valid_sources[0x28]	758	1			T25	74		T35	1		T26	1
valid_sources[0x29]	1271	1			T26	12		T150	2		T48	21
valid_sources[0x2a]	903	1			T69	1		T6	1		T25	1
valid_sources[0x2b]	829	1			T22	6		T26	4		T147	1
valid_sources[0x2c]	629	1			T141	1		T147	1		T48	17
valid_sources[0x2d]	838	1			T24	1		T14	4		T141	2
valid_sources[0x2e]	927	1			T6	1		T25	3		T26	4
valid_sources[0x2f]	712	1			T6	1		T25	64		T55	1
valid_sources[0x30]	888	1			T24	2		T25	1		T147	1
valid_sources[0x31]	671	1			T4	1		T51	1		T48	21
valid_sources[0x32]	600	1			T26	1		T48	37		T151	1
valid_sources[0x33]	613	1			T4	3		T8	3		T6	2
valid_sources[0x34]	1040	1			T25	3		T26	1		T139	3
valid_sources[0x35]	585	1			T26	2		T48	31		T49	1
valid_sources[0x36]	576	1			T26	5		T48	24		T66	11
valid_sources[0x37]	924	1			T26	7		T147	1		T152	1
valid_sources[0x38]	1474	1			T12	1		T25	2		T141	1
valid_sources[0x39]	761	1			T53	2		T147	1		T48	19
valid_sources[0x3a]	1090	1			T4	2		T24	3		T6	1
valid_sources[0x3b]	586	1			T4	2		T25	3		T26	1
valid_sources[0x3c]	1320	1			T24	1		T6	1		T25	3
valid_sources[0x3d]	947	1			T6	1		T25	1		T26	8
valid_sources[0x3e]	967	1			T26	5		T147	1		T48	20
valid_sources[0x3f]	789	1			T24	1		T26	17		T48	29
valid_sources[0x40]	934	1			T24	1		T7	71		T35	1
valid_sources[0x41]	973	1			T24	44		T27	1		T6	1
valid_sources[0x42]	763	1			T6	2		T25	1		T39	1
valid_sources[0x43]	994	1			T26	1		T147	1		T153	1
valid_sources[0x44]	1103	1			T5	2		T35	1		T26	7
valid_sources[0x45]	945	1			T25	54		T26	9		T48	20
valid_sources[0x46]	1057	1			T27	1		T26	5		T154	2
valid_sources[0x47]	1050	1			T25	1		T39	1		T26	10
valid_sources[0x48]	726	1			T26	13		T48	14		T49	1
valid_sources[0x49]	982	1			T24	129		T26	3		T48	22
valid_sources[0x4a]	1059	1			T65	1		T26	27		T48	29
valid_sources[0x4b]	1005	1			T24	2		T35	1		T26	19
valid_sources[0x4c]	1107	1			T6	3		T25	2		T51	1
valid_sources[0x4d]	904	1			T24	2		T6	1		T39	1
valid_sources[0x4e]	689	1			T24	1		T25	1		T15	2
valid_sources[0x4f]	650	1			T25	4		T48	24		T66	13
valid_sources[0x50]	691	1			T24	1		T139	2		T149	1
valid_sources[0x51]	1061	1			T6	1		T25	1		T26	22
valid_sources[0x52]	794	1			T69	1		T26	2		T48	20
valid_sources[0x53]	834	1			T6	2		T25	1		T48	27
valid_sources[0x54]	899	1			T24	1		T6	1		T25	63
valid_sources[0x55]	751	1			T4	1		T65	3		T26	5
valid_sources[0x56]	874	1			T24	3		T25	1		T39	1
valid_sources[0x57]	789	1			T26	8		T139	1		T48	23
valid_sources[0x58]	837	1			T25	2		T26	9		T48	24
valid_sources[0x59]	581	1			T48	12		T49	1		T50	5
valid_sources[0x5a]	806	1			T25	2		T39	3		T35	1
valid_sources[0x5b]	946	1			T6	2		T25	1		T26	9
valid_sources[0x5c]	632	1			T25	1		T48	11		T155	2
valid_sources[0x5d]	880	1			T24	1		T25	2		T26	1
valid_sources[0x5e]	1000	1			T25	3		T39	1		T35	1
valid_sources[0x5f]	898	1			T26	1		T147	1		T48	14
valid_sources[0x60]	796	1			T15	1		T48	17		T49	2
valid_sources[0x61]	828	1			T25	66		T54	1		T65	2
valid_sources[0x62]	761	1			T24	4		T6	2		T35	1
valid_sources[0x63]	921	1			T141	1		T26	2		T147	1
valid_sources[0x64]	1177	1			T156	9		T26	2		T147	1
valid_sources[0x65]	682	1			T6	1		T48	31		T151	1
valid_sources[0x66]	935	1			T24	2		T25	57		T26	1
valid_sources[0x67]	996	1			T27	1		T26	6		T147	1
valid_sources[0x68]	579	1			T141	1		T26	2		T147	1
valid_sources[0x69]	1019	1			T12	1		T24	1		T27	1
valid_sources[0x6a]	975	1			T24	138		T25	3		T141	1
valid_sources[0x6b]	880	1			T25	79		T123	12		T48	30
valid_sources[0x6c]	829	1			T18	4		T25	1		T26	8
valid_sources[0x6d]	817	1			T25	2		T139	6		T48	21
valid_sources[0x6e]	605	1			T6	2		T26	9		T139	3
valid_sources[0x6f]	841	1			T4	1		T25	1		T26	4
valid_sources[0x70]	793	1			T4	2		T24	28		T51	1
valid_sources[0x71]	762	1			T18	4		T6	1		T39	2
valid_sources[0x72]	955	1			T4	2		T69	1		T25	171
valid_sources[0x73]	586	1			T4	1		T25	2		T26	1
valid_sources[0x74]	786	1			T26	7		T147	1		T157	1
valid_sources[0x75]	689	1			T3	2		T6	1		T141	1
valid_sources[0x76]	914	1			T69	1		T6	1		T15	1
valid_sources[0x77]	569	1			T5	29		T23	1		T25	1
valid_sources[0x78]	614	1			T6	1		T103	4		T26	9
valid_sources[0x79]	694	1			T4	1		T5	27		T23	1
valid_sources[0x7a]	929	1			T141	2		T35	1		T105	1
valid_sources[0x7b]	1213	1			T8	1		T35	1		T26	12
valid_sources[0x7c]	969	1			T27	2		T25	1		T26	4
valid_sources[0x7d]	840	1			T24	2		T6	1		T39	1
valid_sources[0x7e]	801	1			T27	2		T25	1		T51	1
valid_sources[0x7f]	1119	1			T25	163		T26	4		T48	35
valid_sources[0x80]	584	1			T39	4		T48	19		T49	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44628

1

T5

14

T9

6

T24

197

values[0x0]

all_enables

biggest_size

61703

1

T1

6

T3

1

T5

22

values[0x1]

all_enables

biggest_size

59219

1

T8

1

T5

11

T9

2