Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16380763

1

T1

10354

T2

547

T4

37

full_word

144878990

1

T1

193822

T2

5403

T3

10000

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	161259463	1			T1	194857		T2	5950		T3	10000
auto[TlIntgErrCmd]	93	1			T59	5		T60	3		T61	4
auto[TlIntgErrData]	95	1			T59	1		T60	2		T61	5
auto[TlIntgErrBoth]	102	1			T59	4		T60	5		T61	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77712428

1

T1

974381

T2

3016

T3

4983

auto[1]

83547325

1

T1

974193

T2

2934

T3

5017

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8020029	1			T1	5192		T2	288		T4	12
auto[TlIntgErrNone]	partial	auto[1]	8360465	1			T1	5162		T2	259		T4	25
auto[TlIntgErrNone]	full_word	auto[0]	69692261	1			T1	969189		T2	2728		T3	4983
auto[TlIntgErrNone]	full_word	auto[1]	75186708	1			T1	969031		T2	2675		T3	5017
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T60	1		T61	3		T132	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T59	4		T60	2		T61	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T126	1		T131	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T59	1		T134	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T59	1		T60	1		T61	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T60	1		T61	4		T132	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T129	1		T135	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T136	1		T133	1		T137	2
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T59	3		T60	1		T61	5
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T59	1		T60	3		T61	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T127	1		T137	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T60	1		T130	1		T138	1