Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	893485	1			T1	3362		T2	26		T9	39
auto[1]	10692478	1			T1	2310		T2	180		T3	4982
auto[2]	698114	1			T1	2148		T2	13		T9	23
auto[3]	10410483	1			T1	1157		T2	144		T3	5016

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13890278	1			T1	6900		T2	265		T3	9998
auto[1]	2136209	1			T1	834		T2	38		T8	25328
auto[2]	2192491	1			T1	1123		T2	56		T8	25174
auto[3]	4475582	1			T1	120		T2	4		T8	2489

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8860103

1

T1

8976

T2

363

T3

9997

auto[1]

13834457

1

T1

1

T3

1

T8

302085

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	312371	1			T1	2765		T2	19		T9	31
auto[0]	auto[0]	auto[1]	31918	1			T1	272		T2	2		T9	3
auto[0]	auto[0]	auto[2]	32299	1			T1	297		T2	5		T9	3
auto[0]	auto[0]	auto[3]	65619	1			T1	28		T9	2		T12	1726
auto[0]	auto[1]	auto[0]	3106990	1			T1	1765		T2	139		T3	4982
auto[0]	auto[1]	auto[1]	326230	1			T1	341		T2	28		T5	1693
auto[0]	auto[1]	auto[2]	343613	1			T1	178		T2	13		T8	2
auto[0]	auto[1]	auto[3]	390520	1			T1	26		T5	156		T9	3
auto[0]	auto[2]	auto[0]	209416	1			T1	1647		T34	827		T6	7
auto[0]	auto[2]	auto[1]	24496	1			T1	155		T34	96		T38	94
auto[0]	auto[2]	auto[2]	25584	1			T1	310		T2	12		T9	21
auto[0]	auto[2]	auto[3]	47494	1			T1	36		T2	1		T9	2
auto[0]	auto[3]	auto[0]	2929658	1			T1	723		T2	107		T3	5015
auto[0]	auto[3]	auto[1]	321887	1			T1	66		T2	8		T5	1302
auto[0]	auto[3]	auto[2]	337380	1			T1	337		T2	26		T5	1230
auto[0]	auto[3]	auto[3]	354628	1			T1	30		T2	3		T5	106
auto[1]	auto[0]	auto[0]	15056	1			T139	2		T144	649		T120	213
auto[1]	auto[0]	auto[1]	66900	1			T144	2812		T120	997		T145	614
auto[1]	auto[0]	auto[2]	66824	1			T144	2775		T120	1030		T145	647
auto[1]	auto[0]	auto[3]	302498	1			T12	1		T144	12667		T101	4
auto[1]	auto[1]	auto[0]	3654849	1			T8	124424		T10	1480		T23	70425
auto[1]	auto[1]	auto[1]	679864	1			T8	12597		T10	5684		T23	6863
auto[1]	auto[1]	auto[2]	654237	1			T8	12490		T10	6504		T23	7063
auto[1]	auto[1]	auto[3]	1536175	1			T8	1259		T10	26448		T23	713
auto[1]	auto[2]	auto[0]	11046	1			T144	391		T120	125		T146	568
auto[1]	auto[2]	auto[1]	49411	1			T144	1745		T120	621		T146	2539
auto[1]	auto[2]	auto[2]	60004	1			T144	2659		T120	933		T145	579
auto[1]	auto[2]	auto[3]	270663	1			T144	12061		T120	4283		T145	2565
auto[1]	auto[3]	auto[0]	3650892	1			T3	1		T8	124672		T10	1485
auto[1]	auto[3]	auto[1]	635503	1			T8	12731		T10	6456		T23	6879
auto[1]	auto[3]	auto[2]	672550	1			T1	1		T8	12682		T10	5825
auto[1]	auto[3]	auto[3]	1507985	1			T8	1230		T10	26125		T23	689