Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1157614119	242914	0	0
ctrl_regwen_rd_A	1157614119	5280	0	0
exec_rd_A	1157614119	4699	0	0
exec_regwen_rd_A	1157614119	5219	0	0
readback_rd_A	1157614119	3457	0	0
readback_regwen_rd_A	1157614119	2785	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157614119	242914	0	0
T6	174038	0	0	0
T24	27678	2007	0	0
T25	82007	5449	0	0
T26	0	1694	0	0
T27	101462	0	0	0
T34	125121	0	0	0
T42	0	4435	0	0
T43	0	1926	0	0
T48	0	10351	0	0
T51	645686	0	0	0
T52	70212	0	0	0
T56	0	8546	0	0
T66	0	5427	0	0
T67	0	2658	0	0
T68	0	1084	0	0
T69	599205	0	0	0
T70	232918	0	0	0
T71	77962	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157614119	5280	0	0
T42	196496	315	0	0
T43	0	217	0	0
T68	0	90	0	0
T107	0	213	0	0
T108	0	132	0	0
T109	0	123	0	0
T110	0	114	0	0
T111	0	126	0	0
T112	0	191	0	0
T113	0	629	0	0
T114	251022	0	0	0
T115	797974	0	0	0
T116	104384	0	0	0
T117	220117	0	0	0
T118	958	0	0	0
T119	67541	0	0	0
T120	923262	0	0	0
T121	1473	0	0	0
T122	449505	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157614119	4699	0	0
T42	196496	332	0	0
T43	0	168	0	0
T68	0	136	0	0
T107	0	151	0	0
T108	0	85	0	0
T109	0	129	0	0
T110	0	94	0	0
T111	0	123	0	0
T112	0	113	0	0
T113	0	563	0	0
T114	251022	0	0	0
T115	797974	0	0	0
T116	104384	0	0	0
T117	220117	0	0	0
T118	958	0	0	0
T119	67541	0	0	0
T120	923262	0	0	0
T121	1473	0	0	0
T122	449505	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157614119	5219	0	0
T42	196496	356	0	0
T43	0	174	0	0
T68	0	81	0	0
T107	0	252	0	0
T108	0	147	0	0
T109	0	115	0	0
T110	0	110	0	0
T111	0	132	0	0
T112	0	161	0	0
T113	0	689	0	0
T114	251022	0	0	0
T115	797974	0	0	0
T116	104384	0	0	0
T117	220117	0	0	0
T118	958	0	0	0
T119	67541	0	0	0
T120	923262	0	0	0
T121	1473	0	0	0
T122	449505	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157614119	3457	0	0
T42	196496	358	0	0
T43	0	177	0	0
T68	0	109	0	0
T107	0	230	0	0
T108	0	96	0	0
T109	0	70	0	0
T110	0	93	0	0
T111	0	147	0	0
T112	0	136	0	0
T113	0	551	0	0
T114	251022	0	0	0
T115	797974	0	0	0
T116	104384	0	0	0
T117	220117	0	0	0
T118	958	0	0	0
T119	67541	0	0	0
T120	923262	0	0	0
T121	1473	0	0	0
T122	449505	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157614119	2785	0	0
T42	196496	278	0	0
T43	0	89	0	0
T68	0	44	0	0
T107	0	161	0	0
T108	0	68	0	0
T109	0	122	0	0
T110	0	64	0	0
T111	0	98	0	0
T112	0	134	0	0
T113	0	406	0	0
T114	251022	0	0	0
T115	797974	0	0	0
T116	104384	0	0	0
T117	220117	0	0	0
T118	958	0	0	0
T119	67541	0	0	0
T120	923262	0	0	0
T121	1473	0	0	0
T122	449505	0	0	0