Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16642158	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

161312252

1

T1

1613

T2

121418

T3

98303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87743097	1			T1	4295		T2	66715		T3	32768
values[0x0]	43448998	1			T1	1404		T2	32101		T3	32731
values[0x1]	46762315	1			T1	2807		T2	34719		T3	32804

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8446380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

169508030

1

T1

5097

T2

127542

T3

98303

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	593112	1			T1	33		T3	367		T4	623
valid_sources[0x01]	2328931	1			T1	19		T3	363		T4	589
valid_sources[0x02]	1278791	1			T1	32		T3	384		T4	606
valid_sources[0x03]	565993	1			T1	35		T3	390		T4	757
valid_sources[0x04]	556206	1			T1	70		T3	404		T4	630
valid_sources[0x05]	564740	1			T1	54		T3	371		T4	647
valid_sources[0x06]	558844	1			T1	53		T3	367		T4	583
valid_sources[0x07]	577639	1			T1	13		T3	399		T4	663
valid_sources[0x08]	597031	1			T1	36		T3	410		T4	669
valid_sources[0x09]	1207387	1			T1	29		T3	437		T4	664
valid_sources[0x0a]	557809	1			T1	90		T3	356		T4	579
valid_sources[0x0b]	563685	1			T1	103		T3	341		T4	558
valid_sources[0x0c]	1828690	1			T1	44		T3	374		T4	612
valid_sources[0x0d]	559591	1			T1	8		T3	390		T4	602
valid_sources[0x0e]	546201	1			T1	23		T3	359		T4	744
valid_sources[0x0f]	541742	1			T1	37		T3	398		T4	756
valid_sources[0x10]	578186	1			T1	35		T3	376		T4	655
valid_sources[0x11]	562786	1			T1	24		T3	403		T4	615
valid_sources[0x12]	539404	1			T1	44		T3	384		T4	517
valid_sources[0x13]	2204632	1			T1	18		T3	363		T4	680
valid_sources[0x14]	537737	1			T1	20		T3	391		T4	601
valid_sources[0x15]	619511	1			T1	40		T3	403		T4	685
valid_sources[0x16]	546359	1			T1	20		T3	393		T4	595
valid_sources[0x17]	621804	1			T1	41		T3	373		T4	580
valid_sources[0x18]	551708	1			T1	13		T3	403		T4	692
valid_sources[0x19]	609918	1			T1	19		T3	382		T4	667
valid_sources[0x1a]	545097	1			T1	8		T3	351		T4	661
valid_sources[0x1b]	543655	1			T1	63		T3	404		T4	647
valid_sources[0x1c]	1863676	1			T1	14		T3	375		T4	649
valid_sources[0x1d]	543656	1			T1	31		T3	417		T4	638
valid_sources[0x1e]	566962	1			T1	30		T3	384		T4	615
valid_sources[0x1f]	594566	1			T1	27		T3	430		T4	611
valid_sources[0x20]	574258	1			T1	33		T3	362		T4	593
valid_sources[0x21]	538970	1			T1	17		T3	381		T4	656
valid_sources[0x22]	538944	1			T1	39		T3	404		T4	713
valid_sources[0x23]	655134	1			T1	15		T3	380		T4	617
valid_sources[0x24]	592823	1			T1	55		T3	374		T4	681
valid_sources[0x25]	629629	1			T1	24		T2	18735		T3	402
valid_sources[0x26]	578996	1			T1	73		T2	21236		T3	394
valid_sources[0x27]	562219	1			T1	56		T3	369		T4	569
valid_sources[0x28]	582367	1			T1	29		T2	39884		T3	398
valid_sources[0x29]	589263	1			T1	26		T3	390		T4	646
valid_sources[0x2a]	575489	1			T1	33		T3	383		T4	565
valid_sources[0x2b]	584904	1			T1	41		T3	393		T4	606
valid_sources[0x2c]	556289	1			T1	57		T2	2824		T3	403
valid_sources[0x2d]	541823	1			T1	16		T3	407		T4	611
valid_sources[0x2e]	569148	1			T1	28		T3	413		T4	728
valid_sources[0x2f]	680471	1			T1	22		T3	388		T4	607
valid_sources[0x30]	609828	1			T1	41		T3	404		T4	688
valid_sources[0x31]	572307	1			T1	51		T3	383		T4	575
valid_sources[0x32]	573131	1			T1	33		T2	16469		T3	382
valid_sources[0x33]	574560	1			T1	34		T3	403		T4	651
valid_sources[0x34]	609872	1			T1	55		T3	370		T4	619
valid_sources[0x35]	611268	1			T1	36		T3	358		T4	628
valid_sources[0x36]	530999	1			T1	18		T3	379		T4	617
valid_sources[0x37]	608475	1			T1	46		T3	364		T4	557
valid_sources[0x38]	1011565	1			T1	11		T3	404		T4	611
valid_sources[0x39]	641299	1			T1	29		T3	393		T4	622
valid_sources[0x3a]	2132536	1			T1	24		T3	383		T4	629
valid_sources[0x3b]	617575	1			T1	30		T3	420		T4	652
valid_sources[0x3c]	599285	1			T1	51		T3	378		T4	576
valid_sources[0x3d]	550685	1			T1	24		T3	378		T4	700
valid_sources[0x3e]	584215	1			T1	20		T3	364		T4	660
valid_sources[0x3f]	562527	1			T1	16		T3	381		T4	731
valid_sources[0x40]	2134799	1			T1	29		T3	354		T4	637
valid_sources[0x41]	543229	1			T1	28		T3	358		T4	706
valid_sources[0x42]	615581	1			T1	58		T3	433		T4	588
valid_sources[0x43]	562635	1			T1	33		T3	397		T4	646
valid_sources[0x44]	583703	1			T1	97		T3	390		T4	685
valid_sources[0x45]	537541	1			T1	34		T3	365		T4	615
valid_sources[0x46]	798208	1			T1	29		T3	364		T4	634
valid_sources[0x47]	593315	1			T1	11		T3	401		T4	603
valid_sources[0x48]	616120	1			T1	58		T3	417		T4	619
valid_sources[0x49]	557862	1			T1	26		T3	401		T4	591
valid_sources[0x4a]	1674835	1			T1	9		T3	385		T4	619
valid_sources[0x4b]	579809	1			T1	41		T3	375		T4	549
valid_sources[0x4c]	560108	1			T1	17		T3	415		T4	636
valid_sources[0x4d]	538356	1			T1	35		T3	417		T4	704
valid_sources[0x4e]	609959	1			T1	15		T3	385		T4	538
valid_sources[0x4f]	545027	1			T1	46		T3	371		T4	656
valid_sources[0x50]	539757	1			T1	13		T3	383		T4	664
valid_sources[0x51]	647512	1			T1	40		T3	393		T4	542
valid_sources[0x52]	1180581	1			T1	41		T2	4624		T3	333
valid_sources[0x53]	693896	1			T1	48		T3	406		T4	564
valid_sources[0x54]	567770	1			T1	81		T3	384		T4	574
valid_sources[0x55]	539526	1			T1	5		T3	353		T4	580
valid_sources[0x56]	550473	1			T1	53		T3	408		T4	683
valid_sources[0x57]	545578	1			T1	36		T3	384		T4	671
valid_sources[0x58]	539536	1			T1	50		T3	390		T4	632
valid_sources[0x59]	548942	1			T1	14		T3	405		T4	725
valid_sources[0x5a]	560544	1			T1	57		T3	380		T4	613
valid_sources[0x5b]	1296244	1			T1	37		T3	351		T4	640
valid_sources[0x5c]	576218	1			T1	16		T3	386		T4	786
valid_sources[0x5d]	558901	1			T1	46		T3	393		T4	599
valid_sources[0x5e]	550496	1			T3	367		T4	618		T9	2029
valid_sources[0x5f]	631842	1			T1	40		T3	385		T4	559
valid_sources[0x60]	549851	1			T1	26		T3	382		T4	622
valid_sources[0x61]	587960	1			T1	48		T3	368		T4	651
valid_sources[0x62]	637516	1			T1	42		T3	383		T4	652
valid_sources[0x63]	2047510	1			T1	14		T3	367		T4	688
valid_sources[0x64]	567797	1			T1	27		T3	365		T4	570
valid_sources[0x65]	556081	1			T1	57		T3	357		T4	637
valid_sources[0x66]	583679	1			T1	16		T3	363		T4	616
valid_sources[0x67]	2030124	1			T1	5		T3	364		T4	593
valid_sources[0x68]	534301	1			T1	30		T3	408		T4	639
valid_sources[0x69]	587030	1			T1	39		T3	371		T4	612
valid_sources[0x6a]	640553	1			T1	53		T3	389		T4	596
valid_sources[0x6b]	593113	1			T1	41		T3	334		T4	716
valid_sources[0x6c]	743779	1			T1	61		T3	391		T4	657
valid_sources[0x6d]	541636	1			T1	34		T3	422		T4	654
valid_sources[0x6e]	622703	1			T1	15		T3	392		T4	652
valid_sources[0x6f]	555816	1			T1	50		T3	394		T4	597
valid_sources[0x70]	1355138	1			T1	23		T3	384		T4	624
valid_sources[0x71]	560108	1			T1	33		T3	371		T4	678
valid_sources[0x72]	587262	1			T1	26		T3	364		T4	544
valid_sources[0x73]	575512	1			T1	14		T3	367		T4	516
valid_sources[0x74]	639571	1			T1	6		T3	384		T4	621
valid_sources[0x75]	548764	1			T1	25		T2	973		T3	388
valid_sources[0x76]	572451	1			T1	34		T3	376		T4	677
valid_sources[0x77]	543898	1			T1	9		T3	381		T4	720
valid_sources[0x78]	542143	1			T1	34		T3	357		T4	806
valid_sources[0x79]	598733	1			T1	33		T3	388		T4	573
valid_sources[0x7a]	1978101	1			T1	49		T2	23		T3	338
valid_sources[0x7b]	539296	1			T1	17		T3	365		T4	585
valid_sources[0x7c]	585077	1			T1	32		T3	335		T4	647
valid_sources[0x7d]	577414	1			T1	2		T3	352		T4	571
valid_sources[0x7e]	1630859	1			T1	8		T3	385		T4	743
valid_sources[0x7f]	660843	1			T1	23		T3	395		T4	637
valid_sources[0x80]	603897	1			T1	10		T3	420		T4	579

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79384943

1

T1

787

T2

60601

T3

32768

values[0x0]

all_enables

biggest_size

40963636

1

T1

398

T2

30325

T3

32731

values[0x1]

all_enables

biggest_size

40963673

1

T1

428

T2

30492

T3

32804

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155605

1

T2

3

T3

59

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55308	1			T26	555		T29	22		T20	26
values[0x0]	70149	1			T2	10		T3	117		T4	12
values[0x1]	75459	1			T1	1		T2	14		T3	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

165910

1

T2

4

T3

77

T4

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	897	1			T11	7		T26	10		T28	3
valid_sources[0x01]	749	1			T3	1		T26	6		T14	21
valid_sources[0x02]	756	1			T3	1		T26	6		T27	1
valid_sources[0x03]	649	1			T3	1		T26	10		T29	8
valid_sources[0x04]	589	1			T26	6		T27	8		T24	8
valid_sources[0x05]	654	1			T26	10		T27	11		T24	7
valid_sources[0x06]	1222	1			T3	1		T26	6		T27	6
valid_sources[0x07]	836	1			T3	1		T26	6		T20	3
valid_sources[0x08]	599	1			T3	1		T26	5		T20	9
valid_sources[0x09]	682	1			T3	1		T4	4		T26	13
valid_sources[0x0a]	564	1			T3	2		T45	1		T26	8
valid_sources[0x0b]	783	1			T26	14		T27	8		T24	3
valid_sources[0x0c]	765	1			T26	6		T20	5		T27	4
valid_sources[0x0d]	1094	1			T3	4		T26	23		T20	1
valid_sources[0x0e]	633	1			T3	1		T26	9		T27	2
valid_sources[0x0f]	705	1			T13	1		T26	12		T27	8
valid_sources[0x10]	741	1			T3	1		T45	2		T26	14
valid_sources[0x11]	670	1			T26	6		T27	4		T24	9
valid_sources[0x12]	1144	1			T26	9		T29	4		T27	7
valid_sources[0x13]	589	1			T26	11		T20	2		T27	8
valid_sources[0x14]	892	1			T26	7		T20	2		T27	1
valid_sources[0x15]	769	1			T26	13		T20	2		T27	10
valid_sources[0x16]	725	1			T3	3		T26	8		T29	6
valid_sources[0x17]	846	1			T26	4		T27	3		T24	4
valid_sources[0x18]	901	1			T3	2		T26	9		T27	7
valid_sources[0x19]	978	1			T3	1		T26	2		T20	3
valid_sources[0x1a]	949	1			T26	6		T20	3		T27	12
valid_sources[0x1b]	714	1			T3	2		T26	2		T27	5
valid_sources[0x1c]	830	1			T26	10		T27	5		T24	22
valid_sources[0x1d]	636	1			T3	2		T45	1		T26	8
valid_sources[0x1e]	915	1			T3	1		T26	5		T20	2
valid_sources[0x1f]	595	1			T26	8		T20	1		T27	3
valid_sources[0x20]	508	1			T26	8		T27	3		T24	21
valid_sources[0x21]	1040	1			T3	1		T11	5		T26	10
valid_sources[0x22]	617	1			T3	1		T26	10		T28	2
valid_sources[0x23]	621	1			T26	6		T27	5		T24	10
valid_sources[0x24]	726	1			T26	8		T27	10		T24	16
valid_sources[0x25]	717	1			T26	8		T27	2		T24	26
valid_sources[0x26]	818	1			T3	1		T4	1		T26	6
valid_sources[0x27]	870	1			T3	1		T26	11		T27	2
valid_sources[0x28]	584	1			T26	12		T27	4		T24	26
valid_sources[0x29]	556	1			T45	1		T26	17		T27	5
valid_sources[0x2a]	981	1			T3	2		T26	12		T20	1
valid_sources[0x2b]	953	1			T2	24		T26	7		T27	6
valid_sources[0x2c]	1269	1			T3	1		T26	9		T28	1
valid_sources[0x2d]	989	1			T26	13		T28	1		T27	6
valid_sources[0x2e]	837	1			T3	1		T26	9		T27	3
valid_sources[0x2f]	1149	1			T4	2		T26	16		T29	7
valid_sources[0x30]	723	1			T26	4		T28	3		T27	22
valid_sources[0x31]	817	1			T26	4		T20	1		T27	6
valid_sources[0x32]	944	1			T3	1		T26	4		T28	1
valid_sources[0x33]	839	1			T45	1		T26	11		T28	1
valid_sources[0x34]	632	1			T11	2		T26	7		T27	4
valid_sources[0x35]	865	1			T3	1		T26	10		T29	3
valid_sources[0x36]	849	1			T3	3		T26	10		T27	7
valid_sources[0x37]	938	1			T26	4		T28	1		T27	7
valid_sources[0x38]	736	1			T3	2		T26	4		T20	2
valid_sources[0x39]	782	1			T45	1		T26	8		T20	2
valid_sources[0x3a]	840	1			T3	2		T4	1		T26	9
valid_sources[0x3b]	740	1			T26	9		T27	2		T24	36
valid_sources[0x3c]	1011	1			T3	2		T26	12		T20	1
valid_sources[0x3d]	797	1			T3	1		T26	7		T20	3
valid_sources[0x3e]	673	1			T3	1		T9	1		T26	5
valid_sources[0x3f]	730	1			T3	1		T26	13		T27	3
valid_sources[0x40]	808	1			T3	2		T26	8		T29	8
valid_sources[0x41]	666	1			T3	3		T26	8		T27	4
valid_sources[0x42]	512	1			T3	1		T26	10		T27	11
valid_sources[0x43]	600	1			T3	2		T44	3		T26	4
valid_sources[0x44]	784	1			T3	1		T26	7		T28	1
valid_sources[0x45]	741	1			T26	7		T27	6		T24	19
valid_sources[0x46]	987	1			T26	9		T29	3		T27	3
valid_sources[0x47]	774	1			T4	1		T26	9		T27	8
valid_sources[0x48]	750	1			T26	8		T27	5		T24	4
valid_sources[0x49]	952	1			T26	5		T27	4		T24	3
valid_sources[0x4a]	776	1			T26	4		T20	1		T28	1
valid_sources[0x4b]	823	1			T3	1		T45	1		T26	8
valid_sources[0x4c]	766	1			T26	11		T27	5		T24	19
valid_sources[0x4d]	688	1			T3	1		T4	1		T26	13
valid_sources[0x4e]	707	1			T45	1		T26	6		T27	6
valid_sources[0x4f]	729	1			T3	1		T26	7		T27	16
valid_sources[0x50]	644	1			T3	1		T26	12		T28	3
valid_sources[0x51]	596	1			T3	2		T26	12		T24	16
valid_sources[0x52]	791	1			T26	8		T29	5		T27	7
valid_sources[0x53]	1341	1			T26	5		T20	1		T27	8
valid_sources[0x54]	1027	1			T26	9		T21	1		T27	2
valid_sources[0x55]	957	1			T3	3		T45	1		T26	8
valid_sources[0x56]	637	1			T1	1		T3	1		T26	5
valid_sources[0x57]	665	1			T26	10		T27	12		T24	28
valid_sources[0x58]	779	1			T3	1		T4	1		T26	8
valid_sources[0x59]	1012	1			T26	11		T21	2		T27	6
valid_sources[0x5a]	1153	1			T3	1		T26	7		T27	5
valid_sources[0x5b]	864	1			T26	13		T20	1		T27	10
valid_sources[0x5c]	810	1			T3	1		T10	1		T26	5
valid_sources[0x5d]	634	1			T3	1		T10	1		T45	1
valid_sources[0x5e]	735	1			T3	2		T26	5		T28	1
valid_sources[0x5f]	663	1			T4	1		T12	24		T26	9
valid_sources[0x60]	837	1			T4	1		T26	8		T27	12
valid_sources[0x61]	650	1			T26	6		T27	4		T24	11
valid_sources[0x62]	609	1			T3	2		T26	8		T29	1
valid_sources[0x63]	647	1			T3	1		T26	9		T27	7
valid_sources[0x64]	1186	1			T26	4		T27	1		T24	23
valid_sources[0x65]	860	1			T45	1		T26	10		T20	2
valid_sources[0x66]	744	1			T26	12		T27	13		T24	6
valid_sources[0x67]	802	1			T26	7		T27	6		T24	11
valid_sources[0x68]	929	1			T3	1		T26	11		T27	10
valid_sources[0x69]	769	1			T26	9		T27	1		T24	3
valid_sources[0x6a]	682	1			T3	3		T26	9		T27	5
valid_sources[0x6b]	664	1			T3	1		T26	9		T28	1
valid_sources[0x6c]	671	1			T3	1		T26	6		T28	1
valid_sources[0x6d]	791	1			T26	8		T27	6		T24	15
valid_sources[0x6e]	908	1			T26	11		T76	1		T27	8
valid_sources[0x6f]	652	1			T3	1		T26	9		T27	15
valid_sources[0x70]	700	1			T3	1		T26	3		T27	9
valid_sources[0x71]	948	1			T3	2		T26	10		T27	1
valid_sources[0x72]	955	1			T3	2		T4	1		T26	7
valid_sources[0x73]	824	1			T26	12		T27	13		T24	5
valid_sources[0x74]	737	1			T26	10		T20	1		T27	7
valid_sources[0x75]	628	1			T26	12		T27	10		T24	7
valid_sources[0x76]	958	1			T3	3		T26	8		T20	3
valid_sources[0x77]	1025	1			T3	2		T26	9		T27	17
valid_sources[0x78]	542	1			T26	8		T29	6		T27	1
valid_sources[0x79]	669	1			T3	1		T26	11		T28	5
valid_sources[0x7a]	638	1			T26	5		T20	1		T27	7
valid_sources[0x7b]	654	1			T3	1		T45	2		T26	9
valid_sources[0x7c]	681	1			T3	2		T26	9		T43	2
valid_sources[0x7d]	696	1			T3	1		T26	9		T20	1
valid_sources[0x7e]	582	1			T26	5		T20	1		T27	10
valid_sources[0x7f]	983	1			T3	3		T26	6		T21	1
valid_sources[0x80]	926	1			T26	10		T28	3		T27	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41946

1

T26

495

T29

11

T20

15

values[0x0]

all_enables

biggest_size

58183

1

T2

1

T3

40

T4

5

values[0x1]

all_enables

biggest_size

55476

1

T2

2

T3

19

T4

4