Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16518404

1

T1

6893

T2

10641

T4

14629

full_word

157925162

1

T1

1613

T2

106537

T3

98303

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	174443276	1			T1	8506		T2	117178		T3	98303
auto[TlIntgErrCmd]	96	1			T72	7		T73	7		T74	11
auto[TlIntgErrData]	82	1			T72	5		T73	6		T74	3
auto[TlIntgErrBoth]	112	1			T72	8		T73	7		T74	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84151680

1

T1

4295

T2

50358

T3

32768

auto[1]

90291886

1

T1

4211

T2

66820

T3

65535

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8070477	1			T1	3508		T2	4638		T4	7385
auto[TlIntgErrNone]	partial	auto[1]	8447653	1			T1	3385		T2	6003		T4	7244
auto[TlIntgErrNone]	full_word	auto[0]	76081072	1			T1	787		T2	45720		T3	32768
auto[TlIntgErrNone]	full_word	auto[1]	81844074	1			T1	826		T2	60817		T3	65535
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T72	4		T73	3		T74	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T72	3		T73	4		T74	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T133	1		T138	1		T139	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T74	1		T140	1		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1			T72	1		T73	2		T74	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T72	4		T73	4		T134	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T74	1		T141	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1			T142	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T72	3		T73	3		T74	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T72	5		T73	4		T74	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T74	2		T140	1		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T134	1		T143	1		T140	1