Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
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Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mem_bkdr_scb 100.00 1 100 1 64 64




Group Instance : mem_bkdr_scb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mem_bkdr_scb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group Instance mem_bkdr_scb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
b2b_access_types_cp 4 0 4 100.00 100 1 1 4
b2b_partial_types_cp 4 0 4 100.00 100 1 1 4
raw_hazard_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance mem_bkdr_scb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_cross 32 0 32 100.00 100 1 1 0


Summary for Variable b2b_access_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_access_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 852531 1 T1 240 T13 19 T29 6967
auto[1] 11040030 1 T1 600 T2 5159 T4 25773
auto[2] 625335 1 T1 127 T13 11 T29 3678
auto[3] 10753243 1 T1 498 T2 3794 T4 25660



Summary for Variable b2b_partial_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_partial_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14139109 1 T1 24 T2 7461 T4 42361
auto[1] 2289369 1 T1 158 T2 698 T4 4292
auto[2] 2302170 1 T1 228 T2 709 T4 4359
auto[3] 4540491 1 T1 1055 T2 85 T4 421



Summary for Variable raw_hazard_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for raw_hazard_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8455534 1 T1 1465 T2 8952 T4 51431
auto[1] 14815605 1 T2 1 T4 2 T10 1



Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for all_cross

Bins
raw_hazard_cpb2b_access_types_cpb2b_partial_types_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 368480 1 T1 9 T13 11 T29 5712
auto[0] auto[0] auto[1] 37633 1 T1 35 T13 3 T29 594
auto[0] auto[0] auto[2] 37720 1 T1 40 T13 4 T29 610
auto[0] auto[0] auto[3] 44462 1 T1 156 T13 1 T29 51
auto[0] auto[1] auto[0] 3058128 1 T1 11 T2 4294 T4 21288
auto[0] auto[1] auto[1] 330448 1 T1 98 T2 388 T4 2110
auto[0] auto[1] auto[2] 320851 1 T1 65 T2 422 T4 2177
auto[0] auto[1] auto[3] 196825 1 T1 426 T2 55 T4 197
auto[0] auto[2] auto[0] 258397 1 T29 3111 T43 25 T66 457
auto[0] auto[2] auto[1] 28535 1 T29 306 T43 140 T66 45
auto[0] auto[2] auto[2] 32448 1 T1 18 T13 11 T29 240
auto[0] auto[2] auto[3] 32383 1 T1 109 T29 21 T43 447
auto[0] auto[3] auto[0] 2897910 1 T1 4 T2 3166 T4 21072
auto[0] auto[3] auto[1] 304494 1 T1 25 T2 310 T4 2182
auto[0] auto[3] auto[2] 328592 1 T1 105 T2 287 T4 2182
auto[0] auto[3] auto[3] 178228 1 T1 364 T2 30 T4 223
auto[1] auto[0] auto[0] 11954 1 T78 141 T68 607 T145 891
auto[1] auto[0] auto[1] 54364 1 T78 600 T68 2616 T145 3920
auto[1] auto[0] auto[2] 54024 1 T78 584 T68 2681 T145 3805
auto[1] auto[0] auto[3] 243894 1 T78 2798 T67 3 T68 11838
auto[1] auto[1] auto[0] 3768462 1 T44 78106 T45 1 T78 243
auto[1] auto[1] auto[1] 758407 1 T44 6728 T78 1919 T68 2984
auto[1] auto[1] auto[2] 744076 1 T44 7820 T78 1211 T68 1688
auto[1] auto[1] auto[3] 1862833 1 T4 1 T44 679 T78 8582
auto[1] auto[2] auto[0] 9414 1 T68 379 T145 828 T146 384
auto[1] auto[2] auto[1] 42436 1 T68 1580 T145 3543 T146 1648
auto[1] auto[2] auto[2] 40287 1 T78 539 T68 2928 T145 2615
auto[1] auto[2] auto[3] 181435 1 T78 2560 T68 12942 T145 11669
auto[1] auto[3] auto[0] 3766364 1 T2 1 T4 1 T44 78621
auto[1] auto[3] auto[1] 733052 1 T44 7800 T78 534 T68 650
auto[1] auto[3] auto[2] 744172 1 T10 1 T44 6920 T78 1831
auto[1] auto[3] auto[3] 1800431 1 T44 712 T78 8398 T86 1

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