Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1187917804	223765	0	0
ctrl_regwen_rd_A	1187917804	6148	0	0
exec_rd_A	1187917804	6374	0	0
exec_regwen_rd_A	1187917804	6761	0	0
readback_rd_A	1187917804	4513	0	0
readback_regwen_rd_A	1187917804	4130	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187917804	223765	0	0
T14	1331	0	0	0
T20	585331	0	0	0
T24	0	6432	0	0
T26	102948	4122	0	0
T27	0	2943	0	0
T28	393886	0	0	0
T29	173818	0	0	0
T30	34613	0	0	0
T43	120438	0	0	0
T46	0	3878	0	0
T48	0	4911	0	0
T57	0	3245	0	0
T76	70320	0	0	0
T77	39147	0	0	0
T78	134893	0	0	0
T79	0	5953	0	0
T80	0	1870	0	0
T81	0	5282	0	0
T82	0	1958	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187917804	6148	0	0
T14	1331	0	0	0
T20	585331	0	0	0
T24	0	484	0	0
T26	102948	170	0	0
T27	0	248	0	0
T28	393886	0	0	0
T29	173818	0	0	0
T30	34613	0	0	0
T43	120438	0	0	0
T47	0	137	0	0
T50	0	322	0	0
T57	0	292	0	0
T65	0	495	0	0
T76	70320	0	0	0
T77	39147	0	0	0
T78	134893	0	0	0
T79	0	420	0	0
T129	0	91	0	0
T130	0	248	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187917804	6374	0	0
T14	1331	0	0	0
T20	585331	0	0	0
T24	0	418	0	0
T26	102948	127	0	0
T27	0	229	0	0
T28	393886	0	0	0
T29	173818	0	0	0
T30	34613	0	0	0
T43	120438	0	0	0
T47	0	173	0	0
T50	0	494	0	0
T57	0	194	0	0
T65	0	586	0	0
T76	70320	0	0	0
T77	39147	0	0	0
T78	134893	0	0	0
T79	0	381	0	0
T129	0	170	0	0
T130	0	220	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187917804	6761	0	0
T14	1331	0	0	0
T20	585331	0	0	0
T24	0	466	0	0
T26	102948	196	0	0
T27	0	217	0	0
T28	393886	0	0	0
T29	173818	0	0	0
T30	34613	0	0	0
T43	120438	0	0	0
T47	0	172	0	0
T50	0	542	0	0
T57	0	275	0	0
T65	0	583	0	0
T76	70320	0	0	0
T77	39147	0	0	0
T78	134893	0	0	0
T79	0	504	0	0
T129	0	133	0	0
T130	0	304	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187917804	4513	0	0
T14	1331	0	0	0
T20	585331	0	0	0
T24	0	450	0	0
T26	102948	158	0	0
T27	0	293	0	0
T28	393886	0	0	0
T29	173818	0	0	0
T30	34613	0	0	0
T43	120438	0	0	0
T47	0	204	0	0
T50	0	331	0	0
T57	0	194	0	0
T65	0	504	0	0
T76	70320	0	0	0
T77	39147	0	0	0
T78	134893	0	0	0
T79	0	466	0	0
T129	0	140	0	0
T130	0	332	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187917804	4130	0	0
T14	1331	0	0	0
T20	585331	0	0	0
T24	0	503	0	0
T26	102948	193	0	0
T27	0	183	0	0
T28	393886	0	0	0
T29	173818	0	0	0
T30	34613	0	0	0
T43	120438	0	0	0
T47	0	122	0	0
T50	0	418	0	0
T57	0	259	0	0
T65	0	380	0	0
T76	70320	0	0	0
T77	39147	0	0	0
T78	134893	0	0	0
T79	0	332	0	0
T129	0	115	0	0
T130	0	190	0	0