Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19987

1

T1

854

T3

20

T6

174

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7609	1			T1	205		T3	20		T6	32
values[0x0]	6478	1			T1	326		T6	72		T7	67
values[0x1]	6817	1			T1	323		T6	70		T7	71

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20455

1

T1

854

T3

20

T6

174

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62	1			T1	5		T7	1		T11	3
valid_sources[0x01]	89	1			T1	2		T7	1		T13	2
valid_sources[0x02]	64	1			T1	4		T11	6		T14	1
valid_sources[0x03]	101	1			T1	3		T7	1		T11	6
valid_sources[0x04]	136	1			T1	3		T7	1		T11	9
valid_sources[0x05]	56	1			T1	1		T11	7		T14	1
valid_sources[0x06]	62	1			T1	3		T17	5		T28	1
valid_sources[0x07]	72	1			T1	4		T5	3		T7	2
valid_sources[0x08]	106	1			T1	7		T14	1		T17	1
valid_sources[0x09]	114	1			T1	4		T3	1		T14	1
valid_sources[0x0a]	59	1			T1	4		T11	1		T12	3
valid_sources[0x0b]	68	1			T1	4		T7	1		T14	2
valid_sources[0x0c]	74	1			T1	1		T12	1		T13	12
valid_sources[0x0d]	135	1			T1	1		T6	82		T7	1
valid_sources[0x0e]	79	1			T1	3		T11	4		T14	5
valid_sources[0x0f]	60	1			T1	3		T7	1		T14	2
valid_sources[0x10]	75	1			T1	1		T7	1		T12	2
valid_sources[0x11]	53	1			T1	5		T28	10		T29	1
valid_sources[0x12]	270	1			T1	6		T5	2		T7	1
valid_sources[0x13]	59	1			T1	4		T7	1		T11	3
valid_sources[0x14]	62	1			T1	6		T7	1		T12	1
valid_sources[0x15]	101	1			T1	2		T7	1		T13	12
valid_sources[0x16]	87	1			T1	2		T14	5		T16	1
valid_sources[0x17]	78	1			T1	4		T14	5		T16	1
valid_sources[0x18]	52	1			T1	1		T14	4		T16	1
valid_sources[0x19]	70	1			T1	2		T7	1		T14	2
valid_sources[0x1a]	60	1			T1	8		T12	9		T14	1
valid_sources[0x1b]	62	1			T1	5		T7	2		T11	2
valid_sources[0x1c]	55	1			T1	4		T7	3		T14	2
valid_sources[0x1d]	84	1			T1	4		T7	1		T11	1
valid_sources[0x1e]	51	1			T1	4		T14	2		T19	1
valid_sources[0x1f]	64	1			T1	4		T7	3		T11	11
valid_sources[0x20]	48	1			T1	3		T7	1		T17	3
valid_sources[0x21]	70	1			T1	7		T11	8		T14	4
valid_sources[0x22]	52	1			T1	1		T7	2		T8	1
valid_sources[0x23]	81	1			T1	3		T3	2		T11	7
valid_sources[0x24]	57	1			T7	2		T11	9		T14	5
valid_sources[0x25]	86	1			T1	5		T11	1		T12	1
valid_sources[0x26]	62	1			T1	6		T7	1		T11	1
valid_sources[0x27]	44	1			T1	3		T14	6		T28	1
valid_sources[0x28]	229	1			T1	1		T7	1		T11	3
valid_sources[0x29]	55	1			T1	1		T11	1		T12	5
valid_sources[0x2a]	62	1			T1	4		T7	1		T12	1
valid_sources[0x2b]	72	1			T1	1		T11	3		T12	1
valid_sources[0x2c]	80	1			T1	8		T3	1		T14	6
valid_sources[0x2d]	68	1			T1	3		T17	2		T28	1
valid_sources[0x2e]	107	1			T1	3		T7	1		T11	3
valid_sources[0x2f]	60	1			T1	5		T3	1		T7	2
valid_sources[0x30]	51	1			T1	4		T3	1		T7	1
valid_sources[0x31]	84	1			T1	2		T7	1		T11	1
valid_sources[0x32]	68	1			T1	2		T3	1		T7	1
valid_sources[0x33]	47	1			T1	4		T12	4		T8	1
valid_sources[0x34]	96	1			T1	2		T9	40		T11	1
valid_sources[0x35]	215	1			T1	7		T12	8		T13	8
valid_sources[0x36]	87	1			T1	3		T7	1		T11	1
valid_sources[0x37]	75	1			T1	3		T11	1		T13	7
valid_sources[0x38]	89	1			T1	6		T7	1		T11	11
valid_sources[0x39]	76	1			T1	5		T3	1		T11	4
valid_sources[0x3a]	52	1			T1	4		T7	1		T14	1
valid_sources[0x3b]	60	1			T1	6		T11	1		T14	3
valid_sources[0x3c]	103	1			T1	7		T7	1		T11	5
valid_sources[0x3d]	131	1			T1	5		T12	3		T13	27
valid_sources[0x3e]	103	1			T1	2		T7	1		T12	1
valid_sources[0x3f]	64	1			T1	1		T5	1		T14	2
valid_sources[0x40]	83	1			T1	5		T7	1		T14	2
valid_sources[0x41]	77	1			T1	3		T11	2		T14	2
valid_sources[0x42]	157	1			T1	6		T6	92		T7	1
valid_sources[0x43]	67	1			T1	7		T3	1		T14	1
valid_sources[0x44]	109	1			T1	7		T7	1		T11	4
valid_sources[0x45]	74	1			T1	3		T7	2		T11	3
valid_sources[0x46]	66	1			T1	4		T12	1		T14	4
valid_sources[0x47]	79	1			T1	1		T11	2		T14	3
valid_sources[0x48]	59	1			T1	3		T7	2		T11	4
valid_sources[0x49]	52	1			T1	2		T5	2		T7	1
valid_sources[0x4a]	53	1			T1	3		T14	2		T28	4
valid_sources[0x4b]	70	1			T1	3		T13	12		T14	1
valid_sources[0x4c]	58	1			T1	1		T7	2		T11	9
valid_sources[0x4d]	82	1			T1	5		T7	2		T12	2
valid_sources[0x4e]	167	1			T1	5		T11	2		T12	7
valid_sources[0x4f]	44	1			T1	2		T7	1		T12	1
valid_sources[0x50]	115	1			T1	5		T11	1		T12	8
valid_sources[0x51]	68	1			T1	2		T14	2		T28	4
valid_sources[0x52]	70	1			T1	2		T11	3		T13	8
valid_sources[0x53]	53	1			T1	6		T7	1		T12	1
valid_sources[0x54]	96	1			T1	5		T7	1		T13	8
valid_sources[0x55]	86	1			T1	6		T5	1		T7	2
valid_sources[0x56]	72	1			T1	1		T11	3		T14	3
valid_sources[0x57]	59	1			T1	6		T7	2		T14	5
valid_sources[0x58]	89	1			T1	1		T14	3		T28	11
valid_sources[0x59]	42	1			T1	3		T11	1		T14	1
valid_sources[0x5a]	63	1			T1	9		T14	5		T28	6
valid_sources[0x5b]	60	1			T1	5		T7	1		T11	1
valid_sources[0x5c]	122	1			T1	2		T11	12		T14	5
valid_sources[0x5d]	73	1			T1	3		T14	3		T28	9
valid_sources[0x5e]	79	1			T1	4		T7	1		T11	4
valid_sources[0x5f]	65	1			T1	3		T7	1		T11	3
valid_sources[0x60]	71	1			T1	1		T11	9		T14	4
valid_sources[0x61]	79	1			T1	4		T11	6		T12	1
valid_sources[0x62]	81	1			T1	4		T3	1		T11	5
valid_sources[0x63]	61	1			T1	2		T14	3		T28	2
valid_sources[0x64]	75	1			T1	2		T11	3		T12	2
valid_sources[0x65]	105	1			T1	4		T11	2		T12	3
valid_sources[0x66]	67	1			T1	1		T11	1		T16	1
valid_sources[0x67]	53	1			T1	6		T14	3		T17	2
valid_sources[0x68]	91	1			T1	3		T7	1		T12	4
valid_sources[0x69]	53	1			T1	2		T7	1		T14	1
valid_sources[0x6a]	86	1			T1	4		T12	2		T14	2
valid_sources[0x6b]	82	1			T1	4		T7	1		T14	4
valid_sources[0x6c]	89	1			T1	2		T3	1		T7	1
valid_sources[0x6d]	54	1			T1	8		T7	1		T14	4
valid_sources[0x6e]	78	1			T1	5		T11	5		T14	7
valid_sources[0x6f]	85	1			T1	1		T12	5		T14	2
valid_sources[0x70]	66	1			T1	1		T7	2		T14	5
valid_sources[0x71]	62	1			T1	5		T7	2		T14	1
valid_sources[0x72]	88	1			T1	3		T7	1		T11	10
valid_sources[0x73]	62	1			T1	4		T8	1		T28	6
valid_sources[0x74]	43	1			T1	3		T14	3		T28	3
valid_sources[0x75]	184	1			T1	4		T7	2		T12	2
valid_sources[0x76]	77	1			T1	2		T7	1		T11	2
valid_sources[0x77]	132	1			T1	4		T7	1		T13	37
valid_sources[0x78]	71	1			T1	1		T7	2		T13	9
valid_sources[0x79]	76	1			T1	6		T7	1		T14	5
valid_sources[0x7a]	61	1			T1	3		T7	1		T8	1
valid_sources[0x7b]	79	1			T1	4		T12	1		T14	2
valid_sources[0x7c]	49	1			T1	7		T11	2		T12	1
valid_sources[0x7d]	90	1			T1	9		T3	1		T7	2
valid_sources[0x7e]	74	1			T1	5		T11	5		T14	2
valid_sources[0x7f]	65	1			T1	1		T11	10		T12	1
valid_sources[0x80]	81	1			T1	1		T17	2		T28	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7135

1

T1

205

T3

20

T6

32

values[0x0]

all_enables

biggest_size

6365

1

T1

326

T6

72

T7

67

values[0x1]

all_enables

biggest_size

6487

1

T1

323

T6

70

T7

71

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15647

1

T1

252

T2

9

T3

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13981	1			T1	76		T2	19		T3	85
values[0x0]	8409	1			T1	95		T2	11		T3	79
values[0x1]	8564	1			T1	122		T2	2		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18971

1

T1

277

T2

12

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	99	1			T1	1		T3	2		T9	3
valid_sources[0x01]	70	1			T1	1		T5	2		T9	4
valid_sources[0x02]	150	1			T3	1		T5	1		T9	1
valid_sources[0x03]	80	1			T1	2		T3	2		T5	3
valid_sources[0x04]	159	1			T1	3		T6	2		T9	1
valid_sources[0x05]	81	1			T3	1		T9	1		T11	2
valid_sources[0x06]	79	1			T1	2		T5	2		T9	3
valid_sources[0x07]	109	1			T1	1		T9	2		T11	4
valid_sources[0x08]	116	1			T1	4		T3	1		T5	2
valid_sources[0x09]	119	1			T1	1		T3	1		T6	1
valid_sources[0x0a]	91	1			T9	1		T10	1		T11	2
valid_sources[0x0b]	89	1			T1	1		T3	2		T9	1
valid_sources[0x0c]	92	1			T1	1		T6	1		T9	1
valid_sources[0x0d]	132	1			T1	2		T3	1		T5	1
valid_sources[0x0e]	94	1			T9	2		T10	1		T11	3
valid_sources[0x0f]	268	1			T3	1		T10	1		T7	2
valid_sources[0x10]	151	1			T6	1		T5	1		T9	1
valid_sources[0x11]	135	1			T1	2		T3	1		T6	2
valid_sources[0x12]	112	1			T1	3		T6	2		T5	1
valid_sources[0x13]	112	1			T3	1		T4	20		T10	2
valid_sources[0x14]	85	1			T1	1		T4	4		T9	1
valid_sources[0x15]	106	1			T5	2		T9	3		T10	1
valid_sources[0x16]	157	1			T1	1		T3	1		T9	2
valid_sources[0x17]	173	1			T1	1		T3	1		T9	2
valid_sources[0x18]	100	1			T3	1		T5	1		T11	6
valid_sources[0x19]	128	1			T1	1		T6	1		T9	4
valid_sources[0x1a]	98	1			T1	3		T3	1		T5	2
valid_sources[0x1b]	136	1			T1	1		T3	4		T5	1
valid_sources[0x1c]	109	1			T6	1		T5	2		T9	3
valid_sources[0x1d]	93	1			T1	1		T5	1		T9	2
valid_sources[0x1e]	111	1			T3	3		T5	1		T9	2
valid_sources[0x1f]	117	1			T1	1		T4	3		T5	2
valid_sources[0x20]	185	1			T1	1		T3	1		T9	5
valid_sources[0x21]	121	1			T1	1		T2	1		T3	1
valid_sources[0x22]	243	1			T1	2		T3	1		T4	2
valid_sources[0x23]	175	1			T1	2		T3	1		T5	2
valid_sources[0x24]	116	1			T3	3		T5	1		T9	1
valid_sources[0x25]	94	1			T1	2		T3	1		T6	1
valid_sources[0x26]	91	1			T1	1		T3	1		T6	1
valid_sources[0x27]	99	1			T3	2		T5	1		T10	1
valid_sources[0x28]	212	1			T6	1		T5	1		T9	1
valid_sources[0x29]	99	1			T1	1		T3	1		T6	1
valid_sources[0x2a]	89	1			T1	1		T3	2		T6	1
valid_sources[0x2b]	137	1			T1	1		T3	1		T4	36
valid_sources[0x2c]	100	1			T9	1		T10	1		T11	1
valid_sources[0x2d]	100	1			T3	1		T9	4		T10	1
valid_sources[0x2e]	139	1			T3	1		T6	1		T9	1
valid_sources[0x2f]	125	1			T6	2		T4	21		T5	1
valid_sources[0x30]	94	1			T1	3		T5	1		T7	1
valid_sources[0x31]	150	1			T3	1		T5	1		T9	2
valid_sources[0x32]	93	1			T1	2		T9	3		T10	2
valid_sources[0x33]	90	1			T3	3		T5	2		T9	1
valid_sources[0x34]	150	1			T1	1		T5	2		T9	1
valid_sources[0x35]	94	1			T2	2		T3	3		T9	3
valid_sources[0x36]	140	1			T1	2		T5	1		T7	2
valid_sources[0x37]	120	1			T9	1		T11	2		T13	3
valid_sources[0x38]	83	1			T1	2		T6	2		T9	1
valid_sources[0x39]	100	1			T5	2		T9	2		T13	1
valid_sources[0x3a]	98	1			T1	4		T3	1		T5	1
valid_sources[0x3b]	75	1			T1	1		T11	1		T12	2
valid_sources[0x3c]	83	1			T1	2		T6	1		T5	1
valid_sources[0x3d]	66	1			T3	1		T10	1		T11	2
valid_sources[0x3e]	106	1			T5	2		T9	1		T10	3
valid_sources[0x3f]	174	1			T3	2		T6	2		T9	1
valid_sources[0x40]	85	1			T1	2		T3	1		T9	2
valid_sources[0x41]	116	1			T1	2		T2	2		T3	1
valid_sources[0x42]	99	1			T1	1		T3	2		T5	1
valid_sources[0x43]	87	1			T1	4		T3	3		T9	3
valid_sources[0x44]	87	1			T3	1		T5	1		T9	3
valid_sources[0x45]	117	1			T5	1		T9	2		T11	4
valid_sources[0x46]	79	1			T9	3		T11	2		T12	2
valid_sources[0x47]	88	1			T1	4		T6	2		T5	1
valid_sources[0x48]	107	1			T3	1		T9	5		T7	10
valid_sources[0x49]	120	1			T3	1		T9	1		T10	1
valid_sources[0x4a]	120	1			T1	4		T2	2		T5	2
valid_sources[0x4b]	89	1			T14	1		T30	12		T36	1
valid_sources[0x4c]	156	1			T1	4		T6	2		T4	9
valid_sources[0x4d]	100	1			T1	1		T2	2		T3	3
valid_sources[0x4e]	79	1			T1	3		T3	2		T5	1
valid_sources[0x4f]	91	1			T1	2		T3	1		T5	3
valid_sources[0x50]	70	1			T3	1		T6	1		T9	3
valid_sources[0x51]	116	1			T1	2		T3	1		T9	1
valid_sources[0x52]	107	1			T1	2		T5	3		T10	1
valid_sources[0x53]	80	1			T1	1		T3	1		T5	2
valid_sources[0x54]	152	1			T9	3		T11	3		T26	2
valid_sources[0x55]	142	1			T1	1		T3	1		T4	9
valid_sources[0x56]	110	1			T1	3		T3	1		T6	1
valid_sources[0x57]	159	1			T1	3		T3	1		T5	3
valid_sources[0x58]	192	1			T3	1		T10	1		T11	5
valid_sources[0x59]	271	1			T1	1		T5	2		T9	2
valid_sources[0x5a]	102	1			T3	1		T5	2		T9	2
valid_sources[0x5b]	111	1			T6	2		T5	1		T9	5
valid_sources[0x5c]	121	1			T1	1		T2	3		T5	1
valid_sources[0x5d]	129	1			T1	1		T9	1		T10	1
valid_sources[0x5e]	121	1			T5	4		T9	1		T10	1
valid_sources[0x5f]	124	1			T2	3		T3	2		T6	1
valid_sources[0x60]	153	1			T9	3		T10	1		T7	1
valid_sources[0x61]	175	1			T1	4		T3	1		T6	1
valid_sources[0x62]	115	1			T5	1		T9	3		T11	2
valid_sources[0x63]	481	1			T1	2		T3	4		T5	1
valid_sources[0x64]	124	1			T1	1		T2	2		T9	3
valid_sources[0x65]	65	1			T1	1		T3	2		T6	1
valid_sources[0x66]	102	1			T5	3		T10	3		T11	1
valid_sources[0x67]	96	1			T1	1		T3	3		T6	1
valid_sources[0x68]	74	1			T1	2		T3	2		T6	1
valid_sources[0x69]	127	1			T3	1		T11	3		T14	2
valid_sources[0x6a]	103	1			T9	2		T11	3		T18	1
valid_sources[0x6b]	183	1			T1	1		T3	1		T5	2
valid_sources[0x6c]	101	1			T1	1		T6	1		T5	1
valid_sources[0x6d]	99	1			T5	1		T9	2		T10	1
valid_sources[0x6e]	102	1			T3	2		T6	1		T9	1
valid_sources[0x6f]	97	1			T1	3		T3	2		T6	1
valid_sources[0x70]	116	1			T1	1		T3	1		T6	1
valid_sources[0x71]	92	1			T1	2		T10	2		T11	3
valid_sources[0x72]	97	1			T3	3		T6	1		T5	2
valid_sources[0x73]	129	1			T1	1		T3	3		T6	1
valid_sources[0x74]	109	1			T1	2		T3	2		T10	1
valid_sources[0x75]	100	1			T1	1		T3	1		T4	4
valid_sources[0x76]	124	1			T1	1		T3	1		T5	1
valid_sources[0x77]	99	1			T1	3		T3	1		T6	1
valid_sources[0x78]	245	1			T3	3		T6	2		T9	2
valid_sources[0x79]	117	1			T1	2		T3	2		T5	2
valid_sources[0x7a]	187	1			T1	2		T3	1		T6	2
valid_sources[0x7b]	118	1			T1	1		T3	1		T5	3
valid_sources[0x7c]	89	1			T1	1		T6	3		T9	2
valid_sources[0x7d]	91	1			T1	1		T3	2		T5	2
valid_sources[0x7e]	109	1			T1	1		T3	1		T5	3
valid_sources[0x7f]	96	1			T1	2		T3	1		T5	1
valid_sources[0x80]	235	1			T1	1		T9	6		T7	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6035

1

T1

66

T2

3

T3

17

values[0x0]

all_enables

biggest_size

5189

1

T1

91

T2

5

T3

25

values[0x1]

all_enables

biggest_size

4423

1

T1

95

T2

1

T3

11