Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13700

1

T1

405

T6

408

T7

159

full_word

21586

1

T1

921

T3

20

T6

218

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34986	1			T1	1326		T3	20		T6	626
auto[TlIntgErrCmd]	108	1			T13	7		T17	4		T40	4
auto[TlIntgErrData]	96	1			T13	8		T17	4		T40	2
auto[TlIntgErrBoth]	96	1			T13	5		T17	2		T40	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10536

1

T1

298

T3

20

T6

127

auto[1]

24750

1

T1

1028

T6

499

T7

297

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2914	1			T1	74		T6	87		T7	28
auto[TlIntgErrNone]	partial	auto[1]	10520	1			T1	331		T6	321		T7	131
auto[TlIntgErrNone]	full_word	auto[0]	7483	1			T1	224		T3	20		T6	40
auto[TlIntgErrNone]	full_word	auto[1]	14069	1			T1	697		T6	178		T7	166
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T13	4		T17	1		T40	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T13	3		T17	3		T40	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T53	1		T56	1		T57	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T29	1		T54	2		T58	2
auto[TlIntgErrData]	partial	auto[0]	38	1			T13	4		T17	1		T40	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T13	4		T17	2		T40	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T54	1		T53	1		T59	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T17	1		T29	1		T54	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T13	4		T40	3		T29	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T13	1		T17	2		T40	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T59	1		T60	2		T50	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T53	1		T51	1		-	-