Unified Coverage Report :: Module :: tlul_rsp_intg_gen

Module : tlul_rsp_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78	55.56					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen	0.00	0.00
tb.dut.u_tlul_adapter_sram.u_rsp_gen	0.00	0.00
tb.dut.u_reg_regs.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	0.00	0.00
gen_rsp_intg.u_rsp_gen	0.00	0.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rsp_intg.u_rsp_gen	0.00	0.00

---

Module Instance : tb.dut.u_reg_regs.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	96.61			100.00	100.00	u_reg_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.44	100.00	97.78			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_regs.u_rsp_intg_gen

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
43	0	1
47	0	1
48	0	1
49	0	1
53	0	1

---

Assert Coverage for Module : tlul_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	270	270	0	0
PayLoadWidthCheck	270	270	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	270	270	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	270	270	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	25	1	0	0.00
ALWAYS	47	3	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
47	0	1
48	0	1
49	0	1
53	0	1

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
43	0	1
47	0	1
48	0	1
49	0	1
53	0	1

Line Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	135	135	0	0
PayLoadWidthCheck	135	135	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135	135	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	135	135	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	32	0	0
CONT_ASSIGN	43	0	0
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32		excluded
			Exclude Annotation: [UNR] all inputs are constant
43		excluded
			Exclude Annotation: [UNR] all inputs are constant
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	135	135	0	0
PayLoadWidthCheck	135	135	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135	135	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	135	135	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0