Unified Coverage Report :: Module :: prim_ram_1p_scr

Module : prim_ram_1p_scr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.86	0.00	0.00	95.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_addr_scr.u_prim_subst_perm	0.00	0.00
gen_diffuse_data[0].u_prim_subst_perm_dec	0.00	0.00
gen_diffuse_data[0].u_prim_subst_perm_enc	0.00	0.00
gen_par_scr[0].u_prim_prince	0.00			0.00
u_addr_collision_flop	0.00	0.00				0.00
u_addr_match_buf	0.00	0.00
u_intg_error	0.00	0.00
u_prim_ram_1p_adv	0.00	0.00				0.00
u_read_en_buf	0.00	0.00
u_rvalid_flop	0.00	0.00				0.00
u_write_en_d_buf	0.00	0.00
u_write_en_flop	0.00	0.00				0.00
u_write_pending_flop	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		53	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	154	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
CONT_ASSIGN	190	1	0	0.00
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	206	1	0	0.00
CONT_ASSIGN	211	1	0	0.00
CONT_ASSIGN	232	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	361	1	0	0.00
CONT_ASSIGN	370	1	0	0.00
ALWAYS	376	10	0	0.00
CONT_ASSIGN	404	1	0	0.00
CONT_ASSIGN	448	1	0	0.00
CONT_ASSIGN	449	1	0	0.00
ALWAYS	452	18	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
133	0	1
135	0	1
136	0	1
145	0	1
154	0	1
163	0	1
171	0	1
182	0	1
186	0	1
190	0	1
194	0	1
198	0	1
206	0	1
211	0	1
232	0	1
245	0	1
274	0	1
280	0	1
306	0	1
336	0	1
361	0	1
370	0	1
376	0	1
377	0	1
379	0	1
380	0	1
383	0	1
384	0	1
385	0	1
386	0	1
388	0	1
394	0	1
			==> MISSING_ELSE
404	0	1
448	0	1
449	0	1
452	0	1
453	0	1
454	0	1
455	0	1
456	0	1
457	0	1
458	0	1
459	0	1
461	0	1
463	0	1
464	0	1
			==> MISSING_ELSE
466	0	1
467	0	1
468	0	1
469	0	1
470	0	1
			==> MISSING_ELSE
472	0	1
473	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_ram_1p_scr

	Total	Covered	Percent
Conditions	11	0	0.00
Logical	11	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       133
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       163
 EXPRESSION ((addr_scr == waddr_scr_q) ? MuBi4True : MuBi4False)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       163
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       361
 EXPRESSION (macro_write ? MuBi4False : (rw_collision ? MuBi4True : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       361
 SUB-EXPRESSION (rw_collision ? MuBi4True : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		15	0	0.00
TERNARY	163	2	0	0.00
TERNARY	361	3	0	0.00
IF	379	3	0	0.00
IF	452	7	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	163	((addr_scr == waddr_scr_q)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	361	(macro_write) ? 
-2-:	361	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	379	if (((!intg_error_r_q) && prim_mubi_pkg::mubi4_test_true_loose(rvalid_q)))
-2-:	383	if (prim_mubi_pkg::mubi4_test_true_loose(addr_collision_q))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	452	if ((!rst_ni))
-2-:	463	if (read_en_b)
-3-:	466	if (write_en_b)
-4-:	472	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	-	-	Not Covered
0	-	1	-	Not Covered
0	-	0	-	Not Covered
0	-	-	1	Not Covered
0	-	-	0	Not Covered