Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_integ_handling.u_sync_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_integ_handling.u_sync_fifo_a_size

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		12	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	109	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
109	0	1

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		25	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
ALWAYS	113	7	0	0.00
ALWAYS	125	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
113	0	1
114	0	1
115	0	1
116		unreachable
117	0	1
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
127	0	1
128		unreachable
129	0	1
130	0	1
131	0	1
132	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		25	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
ALWAYS	113	7	0	0.00
ALWAYS	125	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
113	0	1
114	0	1
115	0	1
116		unreachable
117	0	1
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
127	0	1
128		unreachable
129	0	1
130	0	1
131	0	1
132	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	23	0	0.00
Logical	23	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	0	0.00
Logical	20	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	0	0.00
Logical	20	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		3	0	0.00
TERNARY	68	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

---

Branch Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 + Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
0.00	0.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		11	0	0.00
TERNARY	68	3	0	0.00
IF	113	4	0	0.00
IF	125	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		25	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
ALWAYS	113	7	0	0.00
ALWAYS	125	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
113	0	1
114	0	1
115	0	1
116		unreachable
117	0	1
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
127	0	1
128		unreachable
129	0	1
130	0	1
131	0	1
132	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	0	0.00
Logical	20	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		11	0	0.00
TERNARY	68	3	0	0.00
IF	113	4	0	0.00
IF	125	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		25	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
ALWAYS	113	7	0	0.00
ALWAYS	125	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
113	0	1
114	0	1
115	0	1
116		unreachable
117	0	1
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
127	0	1
128		unreachable
129	0	1
130	0	1
131	0	1
132	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	0	0.00
Logical	20	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		11	0	0.00
TERNARY	68	3	0	0.00
IF	113	4	0	0.00
IF	125	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		12	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	109	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
109	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	23	0	0.00
Logical	23	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		3	0	0.00
TERNARY	68	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		12	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	109	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
109	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	23	0	0.00
Logical	23	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		3	0	0.00
TERNARY	68	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		12	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	109	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	0	1
42	0	1
46	0	1
47	0	1
51	0	1
52	0	1
55	0	1
56	0	1
59	0	1
61	0	1
68	0	1
109	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	23	0	0.00
Logical	23	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		3	0	0.00
TERNARY	68	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered