Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.86	0.00	0.00	95.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11323041	13389	0	0
ctrl_regwen_rd_A	11323041	1872	0	0
exec_rd_A	11323041	1846	0	0
exec_regwen_rd_A	11323041	1798	0	0
readback_rd_A	11323041	241	0	0
readback_regwen_rd_A	11323041	235	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11323041	13389	0	0
T1	3615	880	0	0
T2	974	0	0	0
T3	373870	0	0	0
T4	703180	0	0	0
T5	370679	0	0	0
T6	2258	344	0	0
T7	34455	186	0	0
T8	0	11	0	0
T9	707064	0	0	0
T10	1206	0	0	0
T11	6813	420	0	0
T12	0	389	0	0
T13	0	9	0	0
T14	0	364	0	0
T15	0	156	0	0
T16	0	21	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11323041	1872	0	0
T3	373870	21	0	0
T4	703180	0	0	0
T5	370679	43	0	0
T6	2258	0	0	0
T7	34455	0	0	0
T8	0	5	0	0
T9	707064	91	0	0
T10	1206	0	0	0
T11	6813	0	0	0
T12	2052	0	0	0
T13	0	49	0	0
T14	0	40	0	0
T16	0	17	0	0
T18	1151	0	0	0
T25	0	493	0	0
T28	0	10	0	0
T40	0	57	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11323041	1846	0	0
T3	373870	11	0	0
T4	703180	0	0	0
T5	370679	43	0	0
T6	2258	0	0	0
T7	34455	0	0	0
T8	0	8	0	0
T9	707064	80	0	0
T10	1206	0	0	0
T11	6813	0	0	0
T12	2052	0	0	0
T13	0	59	0	0
T14	0	17	0	0
T16	0	2	0	0
T18	1151	0	0	0
T25	0	457	0	0
T28	0	28	0	0
T40	0	45	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11323041	1798	0	0
T3	373870	19	0	0
T4	703180	0	0	0
T5	370679	30	0	0
T6	2258	0	0	0
T7	34455	0	0	0
T8	0	3	0	0
T9	707064	76	0	0
T10	1206	0	0	0
T11	6813	0	0	0
T12	2052	0	0	0
T13	0	65	0	0
T14	0	34	0	0
T16	0	11	0	0
T18	1151	0	0	0
T25	0	460	0	0
T28	0	43	0	0
T40	0	61	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11323041	241	0	0
T14	7607	48	0	0
T15	34734	0	0	0
T16	34842	0	0	0
T17	8533	0	0	0
T19	369832	0	0	0
T26	1448	0	0	0
T27	1217	0	0	0
T28	0	38	0	0
T30	4253	0	0	0
T36	1794	0	0	0
T37	1656	0	0	0
T40	0	7	0	0
T42	0	17	0	0
T43	0	8	0	0
T44	0	5	0	0
T45	0	25	0	0
T46	0	20	0	0
T47	0	6	0	0
T48	0	15	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11323041	235	0	0
T8	35681	3	0	0
T13	15628	0	0	0
T14	7607	33	0	0
T15	34734	0	0	0
T16	0	7	0	0
T25	17477	0	0	0
T26	1448	0	0	0
T27	1217	0	0	0
T28	0	27	0	0
T29	0	5	0	0
T30	4253	0	0	0
T36	1794	0	0	0
T37	1656	0	0	0
T42	0	4	0	0
T43	0	7	0	0
T45	0	68	0	0
T46	0	20	0	0
T49	0	1	0	0