Unified Coverage Report :: Module :: tlul_lc_gate

Module : tlul_lc_gate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_tlul_lc_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.86	0.00	0.00	95.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	0.00	0.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	0.00	0.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	0.00	0.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	0.00	0.00
u_err_en_sync	0.00	0.00
u_state_regs	0.00	0.00				0.00
u_tlul_err_resp	0.00	0.00	0.00			0.00

Line Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
ALWAYS	144	3	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
ALWAYS	153	6	0	0.00
ALWAYS	164	28	0	0.00
ALWAYS	230	10	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	0	1
85	0	1
144	0	3
149	0	1
150	0	1
153	0	1
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
			==> MISSING_ELSE
164	0	1
165	0	1
166	0	1
167	0	1
168	0	1
169	0	1
171	0	1
173	0	1
174	0	1
			==> MISSING_ELSE
176	0	1
177	0	1
			==> MISSING_ELSE
182	0	1
183	0	1
184	0	1
186	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	0	1
202	0	1
203	0	1
			==> MISSING_ELSE
208	0	1
209	0	1
210	0	1
211	0	1
			==> MISSING_ELSE
230	0	1
231	0	1
232	0	1
234	0	1
235	0	1
236	0	1
			==> MISSING_ELSE
239	0	1
240	0	1
241	0	1
242	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : tlul_lc_gate

	Total	Covered	Percent
Conditions	18	0	0.00
Logical	18	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	7	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Not Covered
StError	184	Not Covered
StErrorOutstanding	203	Not Covered
StFlush	184	Not Covered
StOutstanding	174	Not Covered

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Not Covered
StError->StErrorOutstanding	203	Not Covered
StErrorOutstanding->StActive	211	Not Covered
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Not Covered
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		24	0	0.00
IF	144	2	0	0.00
IF	153	4	0	0.00
CASE	171	14	0	0.00
IF	234	2	0	0.00
IF	239	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Not Covered
StActive	0	-	-	-	-	-	-	Not Covered
StActive	-	1	-	-	-	-	-	Not Covered
StActive	-	0	-	-	-	-	-	Not Covered
StOutstanding	-	-	1	-	-	-	-	Not Covered
StOutstanding	-	-	0	-	-	-	-	Not Covered
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Not Covered
StError	-	-	-	-	-	0	-	Not Covered
StErrorOutstanding	-	-	-	-	-	-	1	Not Covered
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		45	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
ALWAYS	144	3	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
ALWAYS	153	6	0	0.00
ALWAYS	164	22	0	0.00
ALWAYS	230	10	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	0	1
85	0	1
144	0	3
149	0	1
150	0	1
153	0	1
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
			==> MISSING_ELSE
164	0	1
165	0	1
166	0	1
167	0	1
168	0	1
169	0	1
171	0	1
173	0	1
174	0	1
			==> MISSING_ELSE
176	0	1
177	0	1
			==> MISSING_ELSE
182	0	1
183	0	1
184	0	1
186	0	1
191		excluded
			Exclude Annotation: VC_COV_UNR
192		excluded
			Exclude Annotation: VC_COV_UNR
193		excluded
			Exclude Annotation: VC_COV_UNR
194		excluded
			Exclude Annotation: VC_COV_UNR
195		excluded
			Exclude Annotation: VC_COV_UNR
196		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
201	0	1
202	0	1
203	0	1
			==> MISSING_ELSE
208	0	1
209	0	1
210	0	1
211	0	1
			==> MISSING_ELSE
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
230	0	1
231	0	1
232	0	1
234	0	1
235	0	1
236	0	1
			==> MISSING_ELSE
239	0	1
240	0	1
241	0	1
242	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
 Exclude Annotation: [LOWRISK] This happens in the 1st cycle after exiting reset. In order to cover it, need to drive TL items during reset, which isn't supported in the agent.

-1-	Status	Tests
0	Excluded
1	Excluded

---

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests	Exclude Annotation
StActive	196	Not Covered
StError	184	Not Covered
StErrorOutstanding	203	Not Covered
StFlush	184	Excluded		VC_COV_UNR
StOutstanding	174	Not Covered

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Not Covered
StError->StErrorOutstanding	203	Not Covered
StErrorOutstanding->StActive	211	Not Covered
StFlush->StActive	196	Excluded
StFlush->StError	194	Excluded
StOutstanding->StError	184	Not Covered
StOutstanding->StFlush	184	Excluded

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		20	0	0.00
IF	144	2	0	0.00
IF	153	4	0	0.00
CASE	171	10	0	0.00
IF	234	2	0	0.00
IF	239	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
StActive	1	-	-	-	-	-	-	Not Covered
StActive	0	-	-	-	-	-	-	Not Covered
StActive	-	1	-	-	-	-	-	Not Covered
StActive	-	0	-	-	-	-	-	Not Covered
StOutstanding	-	-	1	-	-	-	-	Not Covered
StOutstanding	-	-	0	-	-	-	-	Not Covered
StFlush	-	-	-	1	-	-	-	Excluded		VC_COV_UNR
StFlush	-	-	-	0	1	-	-	Excluded		VC_COV_UNR
StFlush	-	-	-	0	0	-	-	Excluded		VC_COV_UNR
StError	-	-	-	-	-	1	-	Not Covered
StError	-	-	-	-	-	0	-	Not Covered
StErrorOutstanding	-	-	-	-	-	-	1	Not Covered
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered