Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_integ_handling.gen_readback_logic.u_rdback_check_flop	0.00	0.00				0.00
gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf	0.00	0.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp	0.00	0.00				0.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp_intg	0.00	0.00				0.00
gen_integ_handling.gen_readback_logic.u_rdback_en_flop	0.00	0.00				0.00
gen_integ_handling.u_sync_fifo	0.00	0.00	0.00			0.00
gen_integ_handling.u_sync_fifo_a_size	0.00	0.00	0.00			0.00
gen_integ_handling.u_tlul_data_integ_enc	0.00	0.00

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		145	0	0.00
ALWAYS	105	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
ALWAYS	239	95	0	0.00
CONT_ASSIGN	506	1	0	0.00
CONT_ASSIGN	517	1	0	0.00
ALWAYS	542	2	0	0.00
ALWAYS	553	0	0
ALWAYS	553	2	0	0.00
ALWAYS	572	2	0	0.00
ALWAYS	579	22	0	0.00
CONT_ASSIGN	633	1	0	0.00
ALWAYS	658	4	0	0.00
CONT_ASSIGN	676	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	716	1	0	0.00
CONT_ASSIGN	717	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	0	1
106	0	1
108	0	1
138	0	1
139	0	1
140	0	1
141	0	1
142	0	1
144	0	1
145	0	1
156	0	1
239	0	1
240	0	1
241	0	1
242	0	1
243	0	1
244	0	1
245	0	1
246	0	1
247	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
253	0	1
255	0	1
257	0	1
262	0	1
263	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
271	0	1
272	0	1
273	0	1
274	0	1
			==> MISSING_ELSE
276	0	1
280	0	1
281	0	1
			==> MISSING_ELSE
284	0	1
287	0	1
			==> MISSING_ELSE
295	0	1
296	0	1
297	0	1
298	0	1
299	0	1
300	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
306	0	1
307	0	1
309	0	1
310	0	1
311	0	1
312	0	1
313	0	1
			==> MISSING_ELSE
320	0	1
322		unreachable
			==> MISSING_ELSE
326	0	1
330	0	1
331	0	1
334	0	1
335	0	1
336	0	1
337	0	1
340	0	1
343	0	1
			==> MISSING_ELSE
350	0	1
352		unreachable
			==> MISSING_ELSE
355	0	1
357	0	1
359	0	1
365	0	1
367		unreachable
			==> MISSING_ELSE
371	0	1
373	0	1
375	0	1
378	0	1
			==> MISSING_ELSE
385	0	1
387		unreachable
			==> MISSING_ELSE
392	0	1
395	0	1
398	0	1
400	0	1
403	0	1
409	0	1
			==> MISSING_ELSE
417	0	1
419		unreachable
			==> MISSING_ELSE
422	0	1
424	0	1
426	0	1
430	0	1
432		unreachable
			==> MISSING_ELSE
435	0	1
438	0	1
440	0	1
443	0	1
			==> MISSING_ELSE
448	0	1
450		unreachable
			==> MISSING_ELSE
455	0	1
459	0	1
460	0	1
462	0	1
463	0	1
465	0	1
466	0	1
467	0	1
470	0	1
			==> MISSING_ELSE
476	0	1
478		unreachable
			==> MISSING_ELSE
481	0	1
483	0	1
486	0	1
488	0	1
489	0	1
490	0	1
			==> MISSING_ELSE
506	0	1
517	0	1
542	0	1
543	0	1
			==> MISSING_ELSE
553	0	1
554	0	1
572	0	1
573	0	1
579	0	1
581	0	1
590	0	1
591	0	1
593	0	1
596	0	1
598	0	1
602	0	1
603	0	1
605	0	1
606	0	1
607	0	1
608	0	1
610	0	1
612	0	1
614	0	1
617	0	1
618	0	1
620	0	1
621	0	1
			==> MISSING_ELSE
623	0	1
626	0	1
			==> MISSING_ELSE
633	0	1
658	0	1
661	0	1
665	0	1
670	0	1
676	0	1
699	0	1
716	0	1
717	0	1

---

Cond Coverage for Module : tlul_sram_byte

	Total	Covered	Percent
Conditions	101	0	0.00
Logical	101	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       139
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       140
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       141
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       142
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       145
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       156
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       266
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       281
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       297
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       459
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       517
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       542
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       554
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       581
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       590
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       593
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       596
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       596
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       598
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       598
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       603
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       607
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       608
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       614
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       620
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       633
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       661
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       665
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       699
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

FSM Coverage for Module : tlul_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	17	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StByteWrReadBack	403	Not Covered
StByteWrReadBackDWait	409	Not Covered
StByteWrReadBackInit	310	Not Covered
StPassThru	310	Not Covered
StRdReadBack	281	Not Covered
StRdReadBackDWait	470	Not Covered
StWaitRd	274	Not Covered
StWrReadBack	340	Not Covered
StWrReadBackDWait	343	Not Covered
StWrReadBackInit	281	Not Covered
StWriteCmd	300	Not Covered

transitions	Line No.	Covered	Tests
StByteWrReadBack->StPassThru	426	Not Covered
StByteWrReadBackDWait->StByteWrReadBack	443	Not Covered
StByteWrReadBackInit->StByteWrReadBack	403	Not Covered
StByteWrReadBackInit->StByteWrReadBackDWait	409	Not Covered
StPassThru->StRdReadBack	281	Not Covered
StPassThru->StWaitRd	274	Not Covered
StPassThru->StWrReadBackInit	281	Not Covered
StRdReadBack->StPassThru	463	Not Covered
StRdReadBack->StRdReadBackDWait	470	Not Covered
StRdReadBackDWait->StPassThru	486	Not Covered
StWaitRd->StWriteCmd	300	Not Covered
StWrReadBack->StPassThru	359	Not Covered
StWrReadBackDWait->StWrReadBack	378	Not Covered
StWrReadBackInit->StWrReadBack	340	Not Covered
StWrReadBackInit->StWrReadBackDWait	343	Not Covered
StWriteCmd->StByteWrReadBackInit	310	Not Covered
StWriteCmd->StPassThru	310	Not Covered

---

Branch Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
Branches		61	0	0.00
IF	105	2	0	0.00
CASE	255	39	0	0.00
IF	542	2	0	0.00
TERNARY	554	2	0	0.00
IF	590	16	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	255	case (gen_integ_handling.state_q)
-2-:	257	if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-:	266	if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-:	271	if (gen_integ_handling.byte_wr_txn)
-5-:	273	if (gen_integ_handling.byte_req_ack)
-6-:	276	if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-:	281	(gen_integ_handling.wr_txn) ? 
-8-:	284	if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-:	297	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-:	299	if (gen_integ_handling.sram_d_ack)
-11-:	309	if (gen_integ_handling.sram_a_ack)
-12-:	320	if ((EnableReadback == 1'b0))
-13-:	330	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-:	337	if (gen_integ_handling.d_ack)
-15-:	350	if ((EnableReadback == 1'b0))
-16-:	365	if ((EnableReadback == 1'b0))
-17-:	375	if (gen_integ_handling.d_ack)
-18-:	385	if ((EnableReadback == 1'b0))
-19-:	395	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-:	400	if (gen_integ_handling.d_ack)
-21-:	417	if ((EnableReadback == 1'b0))
-22-:	430	if ((EnableReadback == 1'b0))
-23-:	440	if (gen_integ_handling.d_ack)
-24-:	448	if ((EnableReadback == 1'b0))
-25-:	459	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-:	462	if (gen_integ_handling.d_ack)
-27-:	476	if ((EnableReadback == 1'b0))
-28-:	483	if (gen_integ_handling.d_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	Status	Tests
StPassThru	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWriteCmd	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWriteCmd	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Unreachable
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Unreachable
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Unreachable
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	542	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	554	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	590	if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-:	593	(gen_integ_handling.wr_phase) ? 
-3-:	596	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-4-:	598	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-5-:	603	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-6-:	607	(gen_integ_handling.wr_phase) ? 
-7-:	608	(gen_integ_handling.wr_phase) ? 
-8-:	610	if (gen_integ_handling.rd_phase)
-9-:	614	if (((!error_i) || gen_integ_handling.stall_host))
-10-:	623	if (gen_integ_handling.wait_phase)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
1	1	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	-	-	-	-	Not Covered
1	-	1	-	-	-	-	-	-	-	Not Covered
1	-	0	-	-	-	-	-	-	-	Not Covered
1	-	-	1	-	-	-	-	-	-	Not Covered
1	-	-	0	-	-	-	-	-	-	Not Covered
1	-	-	-	1	-	-	-	-	-	Not Covered
1	-	-	-	0	-	-	-	-	-	Not Covered
1	-	-	-	-	1	-	-	-	-	Not Covered
1	-	-	-	-	0	-	-	-	-	Not Covered
1	-	-	-	-	-	1	-	-	-	Not Covered
1	-	-	-	-	-	0	-	-	-	Not Covered
0	-	-	-	-	-	-	1	1	-	Not Covered
0	-	-	-	-	-	-	1	0	-	Not Covered
0	-	-	-	-	-	-	0	-	1	Not Covered
0	-	-	-	-	-	-	0	-	0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		145	0	0.00
ALWAYS	105	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
ALWAYS	239	95	0	0.00
CONT_ASSIGN	506	1	0	0.00
CONT_ASSIGN	517	1	0	0.00
ALWAYS	542	2	0	0.00
ALWAYS	553	0	0
ALWAYS	553	2	0	0.00
ALWAYS	572	2	0	0.00
ALWAYS	579	22	0	0.00
CONT_ASSIGN	633	1	0	0.00
ALWAYS	658	4	0	0.00
CONT_ASSIGN	676	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	716	1	0	0.00
CONT_ASSIGN	717	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	0	1
106	0	1
108	0	1
138	0	1
139	0	1
140	0	1
141	0	1
142	0	1
144	0	1
145	0	1
156	0	1
239	0	1
240	0	1
241	0	1
242	0	1
243	0	1
244	0	1
245	0	1
246	0	1
247	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
253	0	1
255	0	1
257	0	1
262	0	1
263	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
271	0	1
272	0	1
273	0	1
274	0	1
			==> MISSING_ELSE
276	0	1
280	0	1
281	0	1
			==> MISSING_ELSE
284	0	1
287	0	1
			==> MISSING_ELSE
295	0	1
296	0	1
297	0	1
298	0	1
299	0	1
300	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
306	0	1
307	0	1
309	0	1
310	0	1
311	0	1
312	0	1
313	0	1
			==> MISSING_ELSE
320	0	1
322		unreachable
			==> MISSING_ELSE
326	0	1
330	0	1
331	0	1
334	0	1
335	0	1
336	0	1
337	0	1
340	0	1
343	0	1
			==> MISSING_ELSE
350	0	1
352		unreachable
			==> MISSING_ELSE
355	0	1
357	0	1
359	0	1
365	0	1
367		unreachable
			==> MISSING_ELSE
371	0	1
373	0	1
375	0	1
378	0	1
			==> MISSING_ELSE
385	0	1
387		unreachable
			==> MISSING_ELSE
392	0	1
395	0	1
398	0	1
400	0	1
403	0	1
409	0	1
			==> MISSING_ELSE
417	0	1
419		unreachable
			==> MISSING_ELSE
422	0	1
424	0	1
426	0	1
430	0	1
432		unreachable
			==> MISSING_ELSE
435	0	1
438	0	1
440	0	1
443	0	1
			==> MISSING_ELSE
448	0	1
450		unreachable
			==> MISSING_ELSE
455	0	1
459	0	1
460	0	1
462	0	1
463	0	1
465	0	1
466	0	1
467	0	1
470	0	1
			==> MISSING_ELSE
476	0	1
478		unreachable
			==> MISSING_ELSE
481	0	1
483	0	1
486	0	1
488	0	1
489	0	1
490	0	1
			==> MISSING_ELSE
506	0	1
517	0	1
542	0	1
543	0	1
			==> MISSING_ELSE
553	0	1
554	0	1
572	0	1
573	0	1
579	0	1
581	0	1
590	0	1
591	0	1
593	0	1
596	0	1
598	0	1
602	0	1
603	0	1
605	0	1
606	0	1
607	0	1
608	0	1
610	0	1
612	0	1
614	0	1
617	0	1
618	0	1
620	0	1
621	0	1
			==> MISSING_ELSE
623	0	1
626	0	1
			==> MISSING_ELSE
633	0	1
658	0	1
661	0	1
665	0	1
670	0	1
676	0	1
699	0	1
716	0	1
717	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Covered	Percent
Conditions	97	0	0.00
Logical	97	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       139
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       140
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       141
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       142
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       145
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       156
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       266
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       281
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       297
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       459
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       517
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       542
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle
1	0	Not Covered
1	1	Not Covered

 LINE       554
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       581
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       590
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       593
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       596
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       596
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       598
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       598
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       603
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       607
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       608
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       614
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       620
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       633
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       661
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Not Covered
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Not Covered

 LINE       665
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       699
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	17	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StByteWrReadBack	403	Not Covered
StByteWrReadBackDWait	409	Not Covered
StByteWrReadBackInit	310	Not Covered
StPassThru	310	Not Covered
StRdReadBack	281	Not Covered
StRdReadBackDWait	470	Not Covered
StWaitRd	274	Not Covered
StWrReadBack	340	Not Covered
StWrReadBackDWait	343	Not Covered
StWrReadBackInit	281	Not Covered
StWriteCmd	300	Not Covered

transitions	Line No.	Covered	Tests
StByteWrReadBack->StPassThru	426	Not Covered
StByteWrReadBackDWait->StByteWrReadBack	443	Not Covered
StByteWrReadBackInit->StByteWrReadBack	403	Not Covered
StByteWrReadBackInit->StByteWrReadBackDWait	409	Not Covered
StPassThru->StRdReadBack	281	Not Covered
StPassThru->StWaitRd	274	Not Covered
StPassThru->StWrReadBackInit	281	Not Covered
StRdReadBack->StPassThru	463	Not Covered
StRdReadBack->StRdReadBackDWait	470	Not Covered
StRdReadBackDWait->StPassThru	486	Not Covered
StWaitRd->StWriteCmd	300	Not Covered
StWrReadBack->StPassThru	359	Not Covered
StWrReadBackDWait->StWrReadBack	378	Not Covered
StWrReadBackInit->StWrReadBack	340	Not Covered
StWrReadBackInit->StWrReadBackDWait	343	Not Covered
StWriteCmd->StByteWrReadBackInit	310	Not Covered
StWriteCmd->StPassThru	310	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		61	0	0.00
IF	105	2	0	0.00
CASE	255	39	0	0.00
IF	542	2	0	0.00
TERNARY	554	2	0	0.00
IF	590	16	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	255	case (gen_integ_handling.state_q)
-2-:	257	if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-:	266	if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-:	271	if (gen_integ_handling.byte_wr_txn)
-5-:	273	if (gen_integ_handling.byte_req_ack)
-6-:	276	if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-:	281	(gen_integ_handling.wr_txn) ? 
-8-:	284	if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-:	297	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-:	299	if (gen_integ_handling.sram_d_ack)
-11-:	309	if (gen_integ_handling.sram_a_ack)
-12-:	320	if ((EnableReadback == 1'b0))
-13-:	330	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-:	337	if (gen_integ_handling.d_ack)
-15-:	350	if ((EnableReadback == 1'b0))
-16-:	365	if ((EnableReadback == 1'b0))
-17-:	375	if (gen_integ_handling.d_ack)
-18-:	385	if ((EnableReadback == 1'b0))
-19-:	395	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-:	400	if (gen_integ_handling.d_ack)
-21-:	417	if ((EnableReadback == 1'b0))
-22-:	430	if ((EnableReadback == 1'b0))
-23-:	440	if (gen_integ_handling.d_ack)
-24-:	448	if ((EnableReadback == 1'b0))
-25-:	459	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-:	462	if (gen_integ_handling.d_ack)
-27-:	476	if ((EnableReadback == 1'b0))
-28-:	483	if (gen_integ_handling.d_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	Status	Tests
StPassThru	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWriteCmd	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWriteCmd	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Unreachable
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Unreachable
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Unreachable
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	542	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	554	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	590	if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-:	593	(gen_integ_handling.wr_phase) ? 
-3-:	596	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-4-:	598	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-5-:	603	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-6-:	607	(gen_integ_handling.wr_phase) ? 
-7-:	608	(gen_integ_handling.wr_phase) ? 
-8-:	610	if (gen_integ_handling.rd_phase)
-9-:	614	if (((!error_i) || gen_integ_handling.stall_host))
-10-:	623	if (gen_integ_handling.wait_phase)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
1	1	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	-	-	-	-	Not Covered
1	-	1	-	-	-	-	-	-	-	Not Covered
1	-	0	-	-	-	-	-	-	-	Not Covered
1	-	-	1	-	-	-	-	-	-	Not Covered
1	-	-	0	-	-	-	-	-	-	Not Covered
1	-	-	-	1	-	-	-	-	-	Not Covered
1	-	-	-	0	-	-	-	-	-	Not Covered
1	-	-	-	-	1	-	-	-	-	Not Covered
1	-	-	-	-	0	-	-	-	-	Not Covered
1	-	-	-	-	-	1	-	-	-	Not Covered
1	-	-	-	-	-	0	-	-	-	Not Covered
0	-	-	-	-	-	-	1	1	-	Not Covered
0	-	-	-	-	-	-	1	0	-	Not Covered
0	-	-	-	-	-	-	0	-	1	Not Covered
0	-	-	-	-	-	-	0	-	0	Not Covered