Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15591782

1

T1

15102

T2

1596

T3

180576

full_word

159149707

1

T1

149664

T2

6925

T3

40267

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	174741139	1			T1	164766		T2	8521		T3	220843
auto[TlIntgErrCmd]	103	1			T67	9		T68	6		T69	2
auto[TlIntgErrData]	119	1			T67	5		T68	8		T69	6
auto[TlIntgErrBoth]	128	1			T67	6		T68	6		T69	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84281476

1

T1

76747

T2

4303

T3

110713

auto[1]

90460013

1

T1

88019

T2

4218

T3

110130

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7617837	1			T1	7075		T2	806		T3	90746
auto[TlIntgErrNone]	partial	auto[1]	7973623	1			T1	8027		T2	790		T3	89830
auto[TlIntgErrNone]	full_word	auto[0]	76663499	1			T1	69672		T2	3497		T3	19967
auto[TlIntgErrNone]	full_word	auto[1]	82486180	1			T1	79992		T2	3428		T3	20300
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T67	3		T156	1		T153	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T67	6		T68	6		T69	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T154	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T153	1		T154	2		T158	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T67	3		T68	4		T69	3
auto[TlIntgErrData]	partial	auto[1]	62	1			T67	2		T68	4		T69	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T156	2		T153	1		T157	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T160	1		T161	1		T158	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T67	1		T68	3		T69	6
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T67	5		T68	3		T69	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T158	1		T162	1		T159	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T154	1		T161	1		T162	1