Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	794757	1			T1	50		T8	162		T12	5922
auto[1]	11055601	1			T1	569		T2	4301		T3	93031
auto[2]	606858	1			T1	43		T8	75		T12	4276
auto[3]	10776856	1			T1	300		T2	4217		T3	92495

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14563714	1			T1	690		T2	5592		T3	6166
auto[1]	2204349	1			T1	113		T2	1330		T3	27686
auto[2]	2244399	1			T1	144		T2	1279		T3	27962
auto[3]	4221610	1			T1	15		T2	317		T3	123712

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10098836

1

T1

962

T2

8518

T4

10111

auto[1]

13135236

1

T3

185526

T4

1

T11

196813

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	401916	1			T1	45		T8	137		T6	463
auto[0]	auto[0]	auto[1]	41685	1			T1	1		T8	15		T6	49
auto[0]	auto[0]	auto[2]	41308	1			T1	3		T8	10		T6	45
auto[0]	auto[0]	auto[3]	40984	1			T1	1		T6	3		T27	1
auto[0]	auto[1]	auto[0]	3621073	1			T1	436		T2	2797		T4	5353
auto[0]	auto[1]	auto[1]	381791	1			T1	92		T2	698		T4	529
auto[0]	auto[1]	auto[2]	386266	1			T1	34		T2	646		T4	515
auto[0]	auto[1]	auto[3]	316135	1			T1	7		T2	160		T4	55
auto[0]	auto[2]	auto[0]	293178	1			T7	13		T41	456		T81	3286
auto[0]	auto[2]	auto[1]	32461	1			T41	47		T121	3		T81	310
auto[0]	auto[2]	auto[2]	34942	1			T1	40		T8	71		T6	286
auto[0]	auto[2]	auto[3]	29861	1			T1	3		T8	4		T6	31
auto[0]	auto[3]	auto[0]	3434119	1			T1	209		T2	2795		T4	3024
auto[0]	auto[3]	auto[1]	365695	1			T1	20		T2	632		T4	305
auto[0]	auto[3]	auto[2]	386496	1			T1	67		T2	633		T4	306
auto[0]	auto[3]	auto[3]	290926	1			T1	4		T2	157		T4	24
auto[1]	auto[0]	auto[0]	8998	1			T12	217		T122	453		T166	1
auto[1]	auto[0]	auto[1]	39922	1			T12	883		T122	2047		T165	376
auto[1]	auto[0]	auto[2]	39965	1			T12	832		T122	2028		T166	1
auto[1]	auto[0]	auto[3]	179979	1			T12	3990		T122	9183		T165	1862
auto[1]	auto[1]	auto[0]	3401536	1			T3	3061		T4	1		T11	81835
auto[1]	auto[1]	auto[1]	666598	1			T3	13698		T11	7808		T12	2888
auto[1]	auto[1]	auto[2]	662095	1			T3	14046		T11	8365		T12	1634
auto[1]	auto[1]	auto[3]	1620107	1			T3	62226		T11	816		T12	13285
auto[1]	auto[2]	auto[0]	6151	1			T122	246		T167	1		T168	238
auto[1]	auto[2]	auto[1]	27128	1			T122	1237		T168	1078		T169	2459
auto[1]	auto[2]	auto[2]	33267	1			T12	762		T122	2239		T165	379
auto[1]	auto[2]	auto[3]	149870	1			T12	3514		T122	10021		T165	1631
auto[1]	auto[3]	auto[0]	3396743	1			T3	3105		T11	81212		T12	158
auto[1]	auto[3]	auto[1]	649069	1			T3	13988		T11	7997		T12	706
auto[1]	auto[3]	auto[2]	660060	1			T3	13916		T11	7971		T12	2843
auto[1]	auto[3]	auto[3]	1593748	1			T3	61486		T11	809		T12	12985