Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1195027574	232697	0	0
ctrl_regwen_rd_A	1195027574	5138	0	0
exec_rd_A	1195027574	4499	0	0
exec_regwen_rd_A	1195027574	4903	0	0
readback_rd_A	1195027574	3358	0	0
readback_regwen_rd_A	1195027574	2856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195027574	232697	0	0
T21	201490	0	0	0
T24	75094	4578	0	0
T25	156694	8439	0	0
T26	30666	1719	0	0
T30	33799	0	0	0
T53	0	9578	0	0
T56	0	11838	0	0
T75	0	952	0	0
T76	0	1884	0	0
T77	0	3518	0	0
T78	0	1120	0	0
T79	0	1648	0	0
T80	73582	0	0	0
T81	655610	0	0	0
T82	197562	0	0	0
T83	438668	0	0	0
T84	121388	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195027574	5138	0	0
T14	1110	0	0	0
T23	109160	0	0	0
T46	0	487	0	0
T75	24117	119	0	0
T77	0	253	0	0
T138	0	115	0	0
T139	0	210	0	0
T140	0	133	0	0
T141	0	107	0	0
T142	0	249	0	0
T143	0	297	0	0
T144	0	340	0	0
T145	33889	0	0	0
T146	71896	0	0	0
T147	76198	0	0	0
T148	33904	0	0	0
T149	141148	0	0	0
T150	78650	0	0	0
T151	137977	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195027574	4499	0	0
T14	1110	0	0	0
T23	109160	0	0	0
T46	0	387	0	0
T75	24117	49	0	0
T77	0	193	0	0
T138	0	119	0	0
T139	0	162	0	0
T140	0	135	0	0
T141	0	115	0	0
T142	0	209	0	0
T143	0	190	0	0
T144	0	336	0	0
T145	33889	0	0	0
T146	71896	0	0	0
T147	76198	0	0	0
T148	33904	0	0	0
T149	141148	0	0	0
T150	78650	0	0	0
T151	137977	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195027574	4903	0	0
T14	1110	0	0	0
T23	109160	0	0	0
T46	0	433	0	0
T75	24117	39	0	0
T77	0	233	0	0
T138	0	103	0	0
T139	0	185	0	0
T140	0	162	0	0
T141	0	115	0	0
T142	0	227	0	0
T143	0	218	0	0
T144	0	388	0	0
T145	33889	0	0	0
T146	71896	0	0	0
T147	76198	0	0	0
T148	33904	0	0	0
T149	141148	0	0	0
T150	78650	0	0	0
T151	137977	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195027574	3358	0	0
T14	1110	0	0	0
T23	109160	0	0	0
T46	0	424	0	0
T75	24117	62	0	0
T77	0	249	0	0
T138	0	73	0	0
T139	0	174	0	0
T140	0	109	0	0
T141	0	66	0	0
T142	0	163	0	0
T143	0	175	0	0
T144	0	296	0	0
T145	33889	0	0	0
T146	71896	0	0	0
T147	76198	0	0	0
T148	33904	0	0	0
T149	141148	0	0	0
T150	78650	0	0	0
T151	137977	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195027574	2856	0	0
T14	1110	0	0	0
T23	109160	0	0	0
T46	0	372	0	0
T75	24117	65	0	0
T77	0	228	0	0
T138	0	103	0	0
T139	0	112	0	0
T140	0	97	0	0
T141	0	71	0	0
T142	0	119	0	0
T143	0	135	0	0
T144	0	271	0	0
T145	33889	0	0	0
T146	71896	0	0	0
T147	76198	0	0	0
T148	33904	0	0	0
T149	141148	0	0	0
T150	78650	0	0	0
T151	137977	0	0	0