| T798 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3381129147 |
|
|
Aug 15 04:55:07 PM PDT 24 |
Aug 15 04:56:21 PM PDT 24 |
768107100 ps |
| T799 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3511431649 |
|
|
Aug 15 04:53:26 PM PDT 24 |
Aug 15 04:53:41 PM PDT 24 |
2264922439 ps |
| T800 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1997612253 |
|
|
Aug 15 04:53:55 PM PDT 24 |
Aug 15 05:10:34 PM PDT 24 |
21991305004 ps |
| T801 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1508774470 |
|
|
Aug 15 04:54:23 PM PDT 24 |
Aug 15 04:54:55 PM PDT 24 |
1139785984 ps |
| T802 |
/workspace/coverage/default/3.sram_ctrl_bijection.2410836938 |
|
|
Aug 15 04:52:55 PM PDT 24 |
Aug 15 05:42:57 PM PDT 24 |
384980413629 ps |
| T803 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3346224940 |
|
|
Aug 15 04:52:54 PM PDT 24 |
Aug 15 04:55:30 PM PDT 24 |
1498578240 ps |
| T804 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2305445622 |
|
|
Aug 15 04:55:34 PM PDT 24 |
Aug 15 05:02:02 PM PDT 24 |
14628788832 ps |
| T112 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.316178558 |
|
|
Aug 15 04:56:05 PM PDT 24 |
Aug 15 04:58:51 PM PDT 24 |
5808731161 ps |
| T805 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3709572318 |
|
|
Aug 15 04:54:38 PM PDT 24 |
Aug 15 06:04:48 PM PDT 24 |
147617827837 ps |
| T806 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3180750751 |
|
|
Aug 15 04:53:27 PM PDT 24 |
Aug 15 04:53:30 PM PDT 24 |
3073994871 ps |
| T807 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3477580858 |
|
|
Aug 15 04:56:52 PM PDT 24 |
Aug 15 05:02:05 PM PDT 24 |
5473861538 ps |
| T808 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1863544752 |
|
|
Aug 15 04:53:14 PM PDT 24 |
Aug 15 05:44:56 PM PDT 24 |
146724720343 ps |
| T809 |
/workspace/coverage/default/35.sram_ctrl_regwen.3702176655 |
|
|
Aug 15 04:55:36 PM PDT 24 |
Aug 15 05:24:25 PM PDT 24 |
36619488000 ps |
| T810 |
/workspace/coverage/default/20.sram_ctrl_smoke.3977244758 |
|
|
Aug 15 04:53:58 PM PDT 24 |
Aug 15 04:54:50 PM PDT 24 |
3208424669 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2441824462 |
|
|
Aug 15 04:55:10 PM PDT 24 |
Aug 15 04:56:35 PM PDT 24 |
47413598904 ps |
| T812 |
/workspace/coverage/default/44.sram_ctrl_executable.620657039 |
|
|
Aug 15 04:56:46 PM PDT 24 |
Aug 15 05:15:22 PM PDT 24 |
12900315122 ps |
| T813 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.367850461 |
|
|
Aug 15 04:53:03 PM PDT 24 |
Aug 15 04:58:59 PM PDT 24 |
34389279046 ps |
| T814 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3679718860 |
|
|
Aug 15 04:53:13 PM PDT 24 |
Aug 15 04:54:11 PM PDT 24 |
3139648693 ps |
| T815 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2815910897 |
|
|
Aug 15 04:55:35 PM PDT 24 |
Aug 15 04:55:36 PM PDT 24 |
24877009 ps |
| T816 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1669783881 |
|
|
Aug 15 04:53:04 PM PDT 24 |
Aug 15 04:54:19 PM PDT 24 |
2722857419 ps |
| T817 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2872666939 |
|
|
Aug 15 04:52:47 PM PDT 24 |
Aug 15 04:52:55 PM PDT 24 |
11147919862 ps |
| T818 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2455888260 |
|
|
Aug 15 04:57:25 PM PDT 24 |
Aug 15 04:57:25 PM PDT 24 |
19209743 ps |
| T819 |
/workspace/coverage/default/32.sram_ctrl_regwen.1590609793 |
|
|
Aug 15 04:55:09 PM PDT 24 |
Aug 15 05:02:20 PM PDT 24 |
1895811920 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2452066105 |
|
|
Aug 15 04:53:46 PM PDT 24 |
Aug 15 05:08:20 PM PDT 24 |
168907484035 ps |
| T821 |
/workspace/coverage/default/13.sram_ctrl_regwen.1692980096 |
|
|
Aug 15 04:53:32 PM PDT 24 |
Aug 15 05:13:17 PM PDT 24 |
11676636677 ps |
| T822 |
/workspace/coverage/default/27.sram_ctrl_partial_access.287109328 |
|
|
Aug 15 04:54:29 PM PDT 24 |
Aug 15 04:54:35 PM PDT 24 |
701020606 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2623716474 |
|
|
Aug 15 04:53:56 PM PDT 24 |
Aug 15 04:54:21 PM PDT 24 |
637773786 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2491798690 |
|
|
Aug 15 04:55:17 PM PDT 24 |
Aug 15 04:55:18 PM PDT 24 |
36358523 ps |
| T825 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3966332257 |
|
|
Aug 15 04:54:28 PM PDT 24 |
Aug 15 05:00:44 PM PDT 24 |
6390142600 ps |
| T826 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3421326437 |
|
|
Aug 15 04:53:56 PM PDT 24 |
Aug 15 04:55:34 PM PDT 24 |
15264777786 ps |
| T827 |
/workspace/coverage/default/43.sram_ctrl_bijection.1486092204 |
|
|
Aug 15 04:56:36 PM PDT 24 |
Aug 15 05:17:09 PM PDT 24 |
16232199345 ps |
| T828 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.884397901 |
|
|
Aug 15 04:55:37 PM PDT 24 |
Aug 15 04:59:43 PM PDT 24 |
17551438024 ps |
| T829 |
/workspace/coverage/default/34.sram_ctrl_executable.1594120245 |
|
|
Aug 15 04:55:16 PM PDT 24 |
Aug 15 05:15:11 PM PDT 24 |
17372464930 ps |
| T830 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3963806645 |
|
|
Aug 15 04:53:15 PM PDT 24 |
Aug 15 04:53:16 PM PDT 24 |
43859570 ps |
| T831 |
/workspace/coverage/default/31.sram_ctrl_alert_test.601909983 |
|
|
Aug 15 04:55:05 PM PDT 24 |
Aug 15 04:55:05 PM PDT 24 |
17379652 ps |
| T832 |
/workspace/coverage/default/38.sram_ctrl_executable.1348275302 |
|
|
Aug 15 04:55:49 PM PDT 24 |
Aug 15 05:23:02 PM PDT 24 |
45616605621 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3698329827 |
|
|
Aug 15 04:54:46 PM PDT 24 |
Aug 15 04:54:47 PM PDT 24 |
15670449 ps |
| T834 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.4202668236 |
|
|
Aug 15 04:52:55 PM PDT 24 |
Aug 15 04:52:59 PM PDT 24 |
1401186354 ps |
| T835 |
/workspace/coverage/default/20.sram_ctrl_executable.3961252185 |
|
|
Aug 15 04:53:56 PM PDT 24 |
Aug 15 05:17:58 PM PDT 24 |
9724737650 ps |
| T836 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.48590462 |
|
|
Aug 15 04:56:44 PM PDT 24 |
Aug 15 04:57:51 PM PDT 24 |
9891223533 ps |
| T837 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.3690345996 |
|
|
Aug 15 04:54:52 PM PDT 24 |
Aug 15 04:55:45 PM PDT 24 |
8739271490 ps |
| T838 |
/workspace/coverage/default/6.sram_ctrl_regwen.3766678331 |
|
|
Aug 15 04:53:08 PM PDT 24 |
Aug 15 05:04:34 PM PDT 24 |
10571849817 ps |
| T839 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3029604905 |
|
|
Aug 15 04:53:41 PM PDT 24 |
Aug 15 04:54:10 PM PDT 24 |
5334932248 ps |
| T840 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.711141102 |
|
|
Aug 15 04:55:05 PM PDT 24 |
Aug 15 04:55:42 PM PDT 24 |
727935434 ps |
| T841 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3864432054 |
|
|
Aug 15 04:56:45 PM PDT 24 |
Aug 15 05:08:55 PM PDT 24 |
9818128357 ps |
| T842 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3930744612 |
|
|
Aug 15 04:57:25 PM PDT 24 |
Aug 15 04:57:59 PM PDT 24 |
911680186 ps |
| T843 |
/workspace/coverage/default/7.sram_ctrl_regwen.1522124198 |
|
|
Aug 15 04:53:05 PM PDT 24 |
Aug 15 05:11:08 PM PDT 24 |
34742814056 ps |
| T844 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3879364322 |
|
|
Aug 15 04:53:42 PM PDT 24 |
Aug 15 04:54:28 PM PDT 24 |
2221680935 ps |
| T845 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3860536872 |
|
|
Aug 15 04:52:46 PM PDT 24 |
Aug 15 06:20:10 PM PDT 24 |
55015733867 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2732941467 |
|
|
Aug 15 04:53:18 PM PDT 24 |
Aug 15 04:56:03 PM PDT 24 |
6045527097 ps |
| T847 |
/workspace/coverage/default/40.sram_ctrl_bijection.577491555 |
|
|
Aug 15 04:56:14 PM PDT 24 |
Aug 15 05:22:03 PM PDT 24 |
129216133164 ps |
| T848 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2503098831 |
|
|
Aug 15 04:53:15 PM PDT 24 |
Aug 15 04:53:57 PM PDT 24 |
6159129144 ps |
| T849 |
/workspace/coverage/default/43.sram_ctrl_executable.1717959137 |
|
|
Aug 15 04:56:37 PM PDT 24 |
Aug 15 05:13:24 PM PDT 24 |
17692136062 ps |
| T850 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3774873228 |
|
|
Aug 15 04:55:56 PM PDT 24 |
Aug 15 04:57:11 PM PDT 24 |
2883763150 ps |
| T851 |
/workspace/coverage/default/16.sram_ctrl_bijection.1862751743 |
|
|
Aug 15 04:53:42 PM PDT 24 |
Aug 15 05:39:20 PM PDT 24 |
167413987806 ps |
| T852 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2410485172 |
|
|
Aug 15 04:55:06 PM PDT 24 |
Aug 15 05:18:19 PM PDT 24 |
10653126993 ps |
| T853 |
/workspace/coverage/default/36.sram_ctrl_smoke.3238084650 |
|
|
Aug 15 04:55:33 PM PDT 24 |
Aug 15 04:55:37 PM PDT 24 |
1449489553 ps |
| T854 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2902573240 |
|
|
Aug 15 04:54:37 PM PDT 24 |
Aug 15 05:20:12 PM PDT 24 |
18200551727 ps |
| T855 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1595276499 |
|
|
Aug 15 04:55:43 PM PDT 24 |
Aug 15 05:00:33 PM PDT 24 |
48932928570 ps |
| T856 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1600008917 |
|
|
Aug 15 04:52:47 PM PDT 24 |
Aug 15 05:00:08 PM PDT 24 |
12118015126 ps |
| T857 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2950167477 |
|
|
Aug 15 04:54:03 PM PDT 24 |
Aug 15 04:54:04 PM PDT 24 |
16210769 ps |
| T858 |
/workspace/coverage/default/19.sram_ctrl_smoke.517541120 |
|
|
Aug 15 04:53:49 PM PDT 24 |
Aug 15 04:53:58 PM PDT 24 |
675494584 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_alert_test.175364938 |
|
|
Aug 15 04:56:40 PM PDT 24 |
Aug 15 04:56:41 PM PDT 24 |
22512883 ps |
| T860 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1154552258 |
|
|
Aug 15 04:54:53 PM PDT 24 |
Aug 15 04:57:45 PM PDT 24 |
27666356209 ps |
| T861 |
/workspace/coverage/default/39.sram_ctrl_smoke.3368503379 |
|
|
Aug 15 04:55:57 PM PDT 24 |
Aug 15 04:56:09 PM PDT 24 |
3753166866 ps |
| T862 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2109362087 |
|
|
Aug 15 04:53:13 PM PDT 24 |
Aug 15 05:03:39 PM PDT 24 |
111507932477 ps |
| T863 |
/workspace/coverage/default/37.sram_ctrl_regwen.785845703 |
|
|
Aug 15 04:55:41 PM PDT 24 |
Aug 15 05:22:57 PM PDT 24 |
105673638039 ps |
| T864 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.587806271 |
|
|
Aug 15 04:52:47 PM PDT 24 |
Aug 15 04:55:19 PM PDT 24 |
19140729146 ps |
| T865 |
/workspace/coverage/default/29.sram_ctrl_bijection.1225579396 |
|
|
Aug 15 04:54:37 PM PDT 24 |
Aug 15 05:22:00 PM PDT 24 |
106882601203 ps |
| T866 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.42197044 |
|
|
Aug 15 04:57:15 PM PDT 24 |
Aug 15 05:24:30 PM PDT 24 |
17651822110 ps |
| T867 |
/workspace/coverage/default/10.sram_ctrl_executable.601652461 |
|
|
Aug 15 04:53:15 PM PDT 24 |
Aug 15 05:10:36 PM PDT 24 |
30119614680 ps |
| T868 |
/workspace/coverage/default/36.sram_ctrl_executable.3237131802 |
|
|
Aug 15 04:55:34 PM PDT 24 |
Aug 15 05:01:31 PM PDT 24 |
11519153035 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2182590341 |
|
|
Aug 15 04:53:32 PM PDT 24 |
Aug 15 04:53:37 PM PDT 24 |
401212889 ps |
| T870 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3735539183 |
|
|
Aug 15 04:57:33 PM PDT 24 |
Aug 15 04:58:28 PM PDT 24 |
5569841340 ps |
| T871 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2020135318 |
|
|
Aug 15 04:55:58 PM PDT 24 |
Aug 15 06:08:54 PM PDT 24 |
392260413246 ps |
| T872 |
/workspace/coverage/default/48.sram_ctrl_bijection.3189298711 |
|
|
Aug 15 04:57:25 PM PDT 24 |
Aug 15 05:16:17 PM PDT 24 |
61799713670 ps |
| T873 |
/workspace/coverage/default/46.sram_ctrl_regwen.3368590534 |
|
|
Aug 15 04:57:01 PM PDT 24 |
Aug 15 05:15:48 PM PDT 24 |
18462721131 ps |
| T874 |
/workspace/coverage/default/22.sram_ctrl_smoke.171748015 |
|
|
Aug 15 04:53:56 PM PDT 24 |
Aug 15 04:56:00 PM PDT 24 |
3201988016 ps |
| T875 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3359477643 |
|
|
Aug 15 04:52:48 PM PDT 24 |
Aug 15 04:53:30 PM PDT 24 |
14545709978 ps |
| T876 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1944716788 |
|
|
Aug 15 04:57:16 PM PDT 24 |
Aug 15 06:20:14 PM PDT 24 |
164433168288 ps |
| T877 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1395703985 |
|
|
Aug 15 04:56:45 PM PDT 24 |
Aug 15 04:57:23 PM PDT 24 |
23716685277 ps |
| T878 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.495212758 |
|
|
Aug 15 04:55:46 PM PDT 24 |
Aug 15 05:15:47 PM PDT 24 |
12992546793 ps |
| T879 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1593900770 |
|
|
Aug 15 04:56:36 PM PDT 24 |
Aug 15 05:11:33 PM PDT 24 |
39727868193 ps |
| T880 |
/workspace/coverage/default/33.sram_ctrl_smoke.1431105859 |
|
|
Aug 15 04:55:09 PM PDT 24 |
Aug 15 04:55:19 PM PDT 24 |
5783921792 ps |
| T881 |
/workspace/coverage/default/9.sram_ctrl_executable.2421843546 |
|
|
Aug 15 04:53:14 PM PDT 24 |
Aug 15 05:11:45 PM PDT 24 |
10119171806 ps |
| T882 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2267556611 |
|
|
Aug 15 04:53:50 PM PDT 24 |
Aug 15 05:09:39 PM PDT 24 |
10105327574 ps |
| T883 |
/workspace/coverage/default/11.sram_ctrl_stress_all.618246701 |
|
|
Aug 15 04:53:27 PM PDT 24 |
Aug 15 05:56:04 PM PDT 24 |
134718963128 ps |
| T884 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1794901947 |
|
|
Aug 15 04:53:27 PM PDT 24 |
Aug 15 04:53:30 PM PDT 24 |
705170313 ps |
| T885 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.190420065 |
|
|
Aug 15 04:56:44 PM PDT 24 |
Aug 15 05:03:34 PM PDT 24 |
6182516484 ps |
| T886 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1007322967 |
|
|
Aug 15 04:54:10 PM PDT 24 |
Aug 15 05:02:05 PM PDT 24 |
43332199937 ps |
| T887 |
/workspace/coverage/default/41.sram_ctrl_stress_all.4201972706 |
|
|
Aug 15 04:56:19 PM PDT 24 |
Aug 15 06:23:07 PM PDT 24 |
573557365374 ps |
| T888 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1894221207 |
|
|
Aug 15 04:53:49 PM PDT 24 |
Aug 15 04:55:41 PM PDT 24 |
976042255 ps |
| T889 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.4199081970 |
|
|
Aug 15 04:54:09 PM PDT 24 |
Aug 15 04:56:36 PM PDT 24 |
10159297898 ps |
| T890 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.464270346 |
|
|
Aug 15 04:57:01 PM PDT 24 |
Aug 15 05:02:05 PM PDT 24 |
123987337569 ps |
| T891 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2192587181 |
|
|
Aug 15 04:56:06 PM PDT 24 |
Aug 15 04:58:32 PM PDT 24 |
6086849059 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_alert_test.162207723 |
|
|
Aug 15 04:53:57 PM PDT 24 |
Aug 15 04:53:58 PM PDT 24 |
23423089 ps |
| T893 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3802477181 |
|
|
Aug 15 04:55:56 PM PDT 24 |
Aug 15 05:22:26 PM PDT 24 |
31247795172 ps |
| T894 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3131911883 |
|
|
Aug 15 04:55:16 PM PDT 24 |
Aug 15 04:55:20 PM PDT 24 |
693463203 ps |
| T895 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1297282307 |
|
|
Aug 15 04:56:05 PM PDT 24 |
Aug 15 04:56:32 PM PDT 24 |
4552270767 ps |
| T896 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.70173376 |
|
|
Aug 15 04:54:07 PM PDT 24 |
Aug 15 05:03:00 PM PDT 24 |
34225282437 ps |
| T897 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.279174784 |
|
|
Aug 15 04:53:13 PM PDT 24 |
Aug 15 04:58:24 PM PDT 24 |
5202644712 ps |
| T898 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2027003907 |
|
|
Aug 15 04:53:06 PM PDT 24 |
Aug 15 04:57:22 PM PDT 24 |
21883704575 ps |
| T899 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.4099294953 |
|
|
Aug 15 04:56:36 PM PDT 24 |
Aug 15 04:59:07 PM PDT 24 |
2556496501 ps |
| T900 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.500116825 |
|
|
Aug 15 04:53:06 PM PDT 24 |
Aug 15 04:53:41 PM PDT 24 |
11918181561 ps |
| T901 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1808413254 |
|
|
Aug 15 04:54:30 PM PDT 24 |
Aug 15 04:54:38 PM PDT 24 |
917095458 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_partial_access.478212025 |
|
|
Aug 15 04:52:57 PM PDT 24 |
Aug 15 04:53:08 PM PDT 24 |
1908859922 ps |
| T903 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3083830381 |
|
|
Aug 15 04:53:18 PM PDT 24 |
Aug 15 04:53:27 PM PDT 24 |
687009271 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3025751758 |
|
|
Aug 15 04:52:57 PM PDT 24 |
Aug 15 04:58:28 PM PDT 24 |
70112878526 ps |
| T905 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2310131581 |
|
|
Aug 15 04:54:28 PM PDT 24 |
Aug 15 05:27:46 PM PDT 24 |
21321261264 ps |
| T906 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3289072622 |
|
|
Aug 15 04:54:03 PM PDT 24 |
Aug 15 04:57:19 PM PDT 24 |
68042326302 ps |
| T907 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3974605850 |
|
|
Aug 15 04:57:06 PM PDT 24 |
Aug 15 05:02:50 PM PDT 24 |
5750021306 ps |
| T908 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.598605913 |
|
|
Aug 15 04:57:08 PM PDT 24 |
Aug 15 05:02:46 PM PDT 24 |
15025078394 ps |
| T909 |
/workspace/coverage/default/39.sram_ctrl_alert_test.568551625 |
|
|
Aug 15 04:56:13 PM PDT 24 |
Aug 15 04:56:14 PM PDT 24 |
37183640 ps |
| T910 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.101129303 |
|
|
Aug 15 04:53:17 PM PDT 24 |
Aug 15 04:58:46 PM PDT 24 |
65839585572 ps |
| T911 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3579251943 |
|
|
Aug 15 04:55:49 PM PDT 24 |
Aug 15 05:02:16 PM PDT 24 |
16030830461 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1501722547 |
|
|
Aug 15 04:57:33 PM PDT 24 |
Aug 15 04:57:40 PM PDT 24 |
707204185 ps |
| T913 |
/workspace/coverage/default/22.sram_ctrl_executable.2936967206 |
|
|
Aug 15 04:54:03 PM PDT 24 |
Aug 15 05:06:25 PM PDT 24 |
34378242327 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1978981207 |
|
|
Aug 15 04:54:57 PM PDT 24 |
Aug 15 04:55:04 PM PDT 24 |
1358011886 ps |
| T915 |
/workspace/coverage/default/17.sram_ctrl_alert_test.899748242 |
|
|
Aug 15 04:53:40 PM PDT 24 |
Aug 15 04:53:41 PM PDT 24 |
11137355 ps |
| T916 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.154077364 |
|
|
Aug 15 04:54:11 PM PDT 24 |
Aug 15 04:54:49 PM PDT 24 |
21280169260 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1201541862 |
|
|
Aug 15 04:54:19 PM PDT 24 |
Aug 15 04:54:34 PM PDT 24 |
1035977900 ps |
| T918 |
/workspace/coverage/default/9.sram_ctrl_smoke.1963852466 |
|
|
Aug 15 04:53:12 PM PDT 24 |
Aug 15 04:53:17 PM PDT 24 |
1482299293 ps |
| T919 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3547662070 |
|
|
Aug 15 04:53:31 PM PDT 24 |
Aug 15 04:54:43 PM PDT 24 |
3607699389 ps |
| T920 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1126961785 |
|
|
Aug 15 04:52:58 PM PDT 24 |
Aug 15 04:54:55 PM PDT 24 |
2046799011 ps |
| T921 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1311933873 |
|
|
Aug 15 04:53:56 PM PDT 24 |
Aug 15 04:55:34 PM PDT 24 |
3652207627 ps |
| T922 |
/workspace/coverage/default/18.sram_ctrl_stress_all.696433822 |
|
|
Aug 15 04:53:48 PM PDT 24 |
Aug 15 06:32:15 PM PDT 24 |
132855469259 ps |
| T923 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2669069012 |
|
|
Aug 15 04:55:17 PM PDT 24 |
Aug 15 04:57:17 PM PDT 24 |
3425386710 ps |
| T924 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1784606835 |
|
|
Aug 15 04:55:35 PM PDT 24 |
Aug 15 04:55:57 PM PDT 24 |
1608564763 ps |
| T925 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1401002037 |
|
|
Aug 15 04:53:41 PM PDT 24 |
Aug 15 04:53:42 PM PDT 24 |
41738860 ps |
| T926 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.4248059898 |
|
|
Aug 15 04:55:18 PM PDT 24 |
Aug 15 04:59:28 PM PDT 24 |
3946246220 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2596273464 |
|
|
Aug 15 04:53:31 PM PDT 24 |
Aug 15 04:53:34 PM PDT 24 |
359949723 ps |
| T928 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2474748451 |
|
|
Aug 15 04:55:37 PM PDT 24 |
Aug 15 05:04:13 PM PDT 24 |
9889681921 ps |
| T929 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3791508342 |
|
|
Aug 15 04:53:55 PM PDT 24 |
Aug 15 04:53:56 PM PDT 24 |
39178133 ps |
| T930 |
/workspace/coverage/default/47.sram_ctrl_smoke.619868790 |
|
|
Aug 15 04:57:07 PM PDT 24 |
Aug 15 04:57:58 PM PDT 24 |
4818615354 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2921942041 |
|
|
Aug 15 04:53:17 PM PDT 24 |
Aug 15 04:54:38 PM PDT 24 |
3556680355 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.900092127 |
|
|
Aug 15 04:57:26 PM PDT 24 |
Aug 15 04:57:30 PM PDT 24 |
1404923070 ps |
| T933 |
/workspace/coverage/default/37.sram_ctrl_stress_all.2516532016 |
|
|
Aug 15 04:55:43 PM PDT 24 |
Aug 15 05:46:49 PM PDT 24 |
169938848189 ps |
| T934 |
/workspace/coverage/default/5.sram_ctrl_smoke.551805748 |
|
|
Aug 15 04:52:55 PM PDT 24 |
Aug 15 04:53:35 PM PDT 24 |
3966608486 ps |
| T935 |
/workspace/coverage/default/42.sram_ctrl_smoke.573911850 |
|
|
Aug 15 04:56:17 PM PDT 24 |
Aug 15 04:56:40 PM PDT 24 |
1523668209 ps |
| T936 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3889916298 |
|
|
Aug 15 04:54:54 PM PDT 24 |
Aug 15 04:54:55 PM PDT 24 |
33329384 ps |
| T937 |
/workspace/coverage/default/37.sram_ctrl_executable.2052796633 |
|
|
Aug 15 04:55:41 PM PDT 24 |
Aug 15 05:17:52 PM PDT 24 |
13925193217 ps |
| T938 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2561124588 |
|
|
Aug 15 04:56:18 PM PDT 24 |
Aug 15 05:04:22 PM PDT 24 |
63651516193 ps |
| T939 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4013694128 |
|
|
Aug 15 04:56:28 PM PDT 24 |
Aug 15 04:57:29 PM PDT 24 |
1189686069 ps |
| T940 |
/workspace/coverage/default/20.sram_ctrl_bijection.272426367 |
|
|
Aug 15 04:53:56 PM PDT 24 |
Aug 15 05:15:49 PM PDT 24 |
263890242321 ps |
| T941 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4108340094 |
|
|
Aug 15 04:57:08 PM PDT 24 |
Aug 15 04:58:54 PM PDT 24 |
6361492398 ps |
| T942 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1989986420 |
|
|
Aug 15 04:57:07 PM PDT 24 |
Aug 15 04:58:22 PM PDT 24 |
2875329912 ps |
| T943 |
/workspace/coverage/default/21.sram_ctrl_smoke.3194241354 |
|
|
Aug 15 04:53:57 PM PDT 24 |
Aug 15 04:54:08 PM PDT 24 |
3595431511 ps |
| T944 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2386873205 |
|
|
Aug 15 04:55:02 PM PDT 24 |
Aug 15 04:57:00 PM PDT 24 |
1819657516 ps |
| T945 |
/workspace/coverage/default/32.sram_ctrl_executable.1080574987 |
|
|
Aug 15 04:55:01 PM PDT 24 |
Aug 15 04:59:35 PM PDT 24 |
17517491180 ps |
| T946 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.335188139 |
|
|
Aug 15 04:53:49 PM PDT 24 |
Aug 15 05:03:30 PM PDT 24 |
25243173814 ps |
| T947 |
/workspace/coverage/default/1.sram_ctrl_smoke.4053953192 |
|
|
Aug 15 04:52:45 PM PDT 24 |
Aug 15 04:53:03 PM PDT 24 |
1107830176 ps |
| T948 |
/workspace/coverage/default/17.sram_ctrl_smoke.1737107582 |
|
|
Aug 15 04:53:42 PM PDT 24 |
Aug 15 04:53:55 PM PDT 24 |
768680043 ps |
| T71 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1503757166 |
|
|
Aug 15 06:12:23 PM PDT 24 |
Aug 15 06:12:24 PM PDT 24 |
19660151 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1343507461 |
|
|
Aug 15 06:12:20 PM PDT 24 |
Aug 15 06:12:24 PM PDT 24 |
1460408467 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1950026490 |
|
|
Aug 15 06:12:25 PM PDT 24 |
Aug 15 06:12:27 PM PDT 24 |
31301683 ps |
| T951 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3599794731 |
|
|
Aug 15 06:12:14 PM PDT 24 |
Aug 15 06:12:17 PM PDT 24 |
1435026824 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2085707222 |
|
|
Aug 15 06:12:25 PM PDT 24 |
Aug 15 06:12:26 PM PDT 24 |
20042374 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1680796190 |
|
|
Aug 15 06:12:35 PM PDT 24 |
Aug 15 06:12:36 PM PDT 24 |
52212284 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2433382940 |
|
|
Aug 15 06:12:07 PM PDT 24 |
Aug 15 06:12:11 PM PDT 24 |
267816271 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4145856712 |
|
|
Aug 15 06:12:21 PM PDT 24 |
Aug 15 06:12:23 PM PDT 24 |
379723950 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3333141823 |
|
|
Aug 15 06:12:25 PM PDT 24 |
Aug 15 06:12:25 PM PDT 24 |
22956717 ps |
| T131 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2391180125 |
|
|
Aug 15 06:12:43 PM PDT 24 |
Aug 15 06:12:43 PM PDT 24 |
32717182 ps |
| T135 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3748245874 |
|
|
Aug 15 06:12:21 PM PDT 24 |
Aug 15 06:12:22 PM PDT 24 |
13109508 ps |
| T132 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.446165957 |
|
|
Aug 15 06:12:34 PM PDT 24 |
Aug 15 06:12:35 PM PDT 24 |
24130613 ps |
| T136 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3519880714 |
|
|
Aug 15 06:12:22 PM PDT 24 |
Aug 15 06:12:23 PM PDT 24 |
25202082 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.937987304 |
|
|
Aug 15 06:12:14 PM PDT 24 |
Aug 15 06:13:08 PM PDT 24 |
29523481194 ps |
| T137 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3120892175 |
|
|
Aug 15 06:12:16 PM PDT 24 |
Aug 15 06:12:17 PM PDT 24 |
43646927 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3295882181 |
|
|
Aug 15 06:12:11 PM PDT 24 |
Aug 15 06:12:11 PM PDT 24 |
14496305 ps |
| T87 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1937253880 |
|
|
Aug 15 06:12:10 PM PDT 24 |
Aug 15 06:12:11 PM PDT 24 |
68143709 ps |
| T88 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3750226330 |
|
|
Aug 15 06:12:35 PM PDT 24 |
Aug 15 06:13:04 PM PDT 24 |
14791488705 ps |
| T133 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3017952700 |
|
|
Aug 15 06:12:32 PM PDT 24 |
Aug 15 06:12:32 PM PDT 24 |
22859843 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.585383284 |
|
|
Aug 15 06:12:25 PM PDT 24 |
Aug 15 06:12:28 PM PDT 24 |
29136379 ps |
| T67 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2534487982 |
|
|
Aug 15 06:12:30 PM PDT 24 |
Aug 15 06:12:33 PM PDT 24 |
330094348 ps |
| T89 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2142300820 |
|
|
Aug 15 06:12:19 PM PDT 24 |
Aug 15 06:12:20 PM PDT 24 |
12115965 ps |
| T68 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1659230635 |
|
|
Aug 15 06:12:38 PM PDT 24 |
Aug 15 06:12:41 PM PDT 24 |
764118444 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.295810523 |
|
|
Aug 15 06:12:20 PM PDT 24 |
Aug 15 06:12:21 PM PDT 24 |
24147111 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2705202477 |
|
|
Aug 15 06:12:23 PM PDT 24 |
Aug 15 06:12:27 PM PDT 24 |
1405361881 ps |
| T91 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3684692428 |
|
|
Aug 15 06:12:23 PM PDT 24 |
Aug 15 06:12:24 PM PDT 24 |
18682293 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3301779481 |
|
|
Aug 15 06:12:32 PM PDT 24 |
Aug 15 06:12:35 PM PDT 24 |
34454062 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.641844545 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:21 PM PDT 24 |
72334435 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1046613471 |
|
|
Aug 15 06:12:08 PM PDT 24 |
Aug 15 06:12:34 PM PDT 24 |
7504668476 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2339396292 |
|
|
Aug 15 06:12:19 PM PDT 24 |
Aug 15 06:12:20 PM PDT 24 |
41755783 ps |
| T69 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2806750208 |
|
|
Aug 15 06:12:24 PM PDT 24 |
Aug 15 06:12:26 PM PDT 24 |
599830668 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3692655310 |
|
|
Aug 15 06:12:26 PM PDT 24 |
Aug 15 06:12:30 PM PDT 24 |
4891420331 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.97582750 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:18 PM PDT 24 |
126948846 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.117797525 |
|
|
Aug 15 06:12:41 PM PDT 24 |
Aug 15 06:12:42 PM PDT 24 |
33863164 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3311772933 |
|
|
Aug 15 06:12:20 PM PDT 24 |
Aug 15 06:12:21 PM PDT 24 |
31094183 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1357988072 |
|
|
Aug 15 06:12:30 PM PDT 24 |
Aug 15 06:13:00 PM PDT 24 |
4115197891 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2648865740 |
|
|
Aug 15 06:12:11 PM PDT 24 |
Aug 15 06:12:12 PM PDT 24 |
47216157 ps |
| T156 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3925511616 |
|
|
Aug 15 06:12:22 PM PDT 24 |
Aug 15 06:12:24 PM PDT 24 |
908126731 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1724867622 |
|
|
Aug 15 06:12:23 PM PDT 24 |
Aug 15 06:12:24 PM PDT 24 |
20869841 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.985352211 |
|
|
Aug 15 06:12:17 PM PDT 24 |
Aug 15 06:12:18 PM PDT 24 |
12269178 ps |
| T966 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3698174139 |
|
|
Aug 15 06:12:09 PM PDT 24 |
Aug 15 06:12:10 PM PDT 24 |
20029467 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3282298700 |
|
|
Aug 15 06:12:33 PM PDT 24 |
Aug 15 06:12:38 PM PDT 24 |
1284309498 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1823897982 |
|
|
Aug 15 06:12:14 PM PDT 24 |
Aug 15 06:12:44 PM PDT 24 |
13701499624 ps |
| T102 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3588524220 |
|
|
Aug 15 06:13:39 PM PDT 24 |
Aug 15 06:14:33 PM PDT 24 |
14116134738 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1771679410 |
|
|
Aug 15 06:12:23 PM PDT 24 |
Aug 15 06:12:24 PM PDT 24 |
14801406 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.897778538 |
|
|
Aug 15 06:12:23 PM PDT 24 |
Aug 15 06:12:27 PM PDT 24 |
352557636 ps |
| T104 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1657696681 |
|
|
Aug 15 06:12:29 PM PDT 24 |
Aug 15 06:12:30 PM PDT 24 |
40752803 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1381232304 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:19 PM PDT 24 |
102411682 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4231931241 |
|
|
Aug 15 06:12:01 PM PDT 24 |
Aug 15 06:12:57 PM PDT 24 |
27134614409 ps |
| T153 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.280334447 |
|
|
Aug 15 06:12:27 PM PDT 24 |
Aug 15 06:12:30 PM PDT 24 |
703451714 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1359513507 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:22 PM PDT 24 |
355035268 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2029921643 |
|
|
Aug 15 06:12:31 PM PDT 24 |
Aug 15 06:12:32 PM PDT 24 |
18750231 ps |
| T157 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1938973474 |
|
|
Aug 15 06:12:36 PM PDT 24 |
Aug 15 06:12:39 PM PDT 24 |
348390871 ps |
| T972 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3280156668 |
|
|
Aug 15 06:12:31 PM PDT 24 |
Aug 15 06:12:38 PM PDT 24 |
259140349 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1460992769 |
|
|
Aug 15 06:12:24 PM PDT 24 |
Aug 15 06:12:28 PM PDT 24 |
366484594 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3725609562 |
|
|
Aug 15 06:12:14 PM PDT 24 |
Aug 15 06:12:15 PM PDT 24 |
62235146 ps |
| T155 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1412336775 |
|
|
Aug 15 06:12:26 PM PDT 24 |
Aug 15 06:12:28 PM PDT 24 |
1281049639 ps |
| T114 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3999411899 |
|
|
Aug 15 06:12:34 PM PDT 24 |
Aug 15 06:13:00 PM PDT 24 |
3841536059 ps |
| T115 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4252677576 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:19 PM PDT 24 |
32876374 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2908559809 |
|
|
Aug 15 06:12:26 PM PDT 24 |
Aug 15 06:12:27 PM PDT 24 |
13926818 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2607264549 |
|
|
Aug 15 06:12:26 PM PDT 24 |
Aug 15 06:12:28 PM PDT 24 |
28447941 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.32056359 |
|
|
Aug 15 06:12:16 PM PDT 24 |
Aug 15 06:12:17 PM PDT 24 |
49850491 ps |
| T978 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.177334373 |
|
|
Aug 15 06:12:27 PM PDT 24 |
Aug 15 06:12:28 PM PDT 24 |
31379010 ps |
| T126 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3236123323 |
|
|
Aug 15 06:13:43 PM PDT 24 |
Aug 15 06:14:33 PM PDT 24 |
8697651001 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3248700233 |
|
|
Aug 15 06:12:36 PM PDT 24 |
Aug 15 06:12:37 PM PDT 24 |
17944099 ps |
| T980 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1074685920 |
|
|
Aug 15 06:12:39 PM PDT 24 |
Aug 15 06:12:44 PM PDT 24 |
1437801189 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.23113916 |
|
|
Aug 15 06:12:21 PM PDT 24 |
Aug 15 06:12:22 PM PDT 24 |
43343884 ps |
| T127 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2617486818 |
|
|
Aug 15 06:12:24 PM PDT 24 |
Aug 15 06:13:20 PM PDT 24 |
14679334247 ps |
| T982 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4267607759 |
|
|
Aug 15 06:12:28 PM PDT 24 |
Aug 15 06:12:29 PM PDT 24 |
113461160 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4067307896 |
|
|
Aug 15 06:12:08 PM PDT 24 |
Aug 15 06:12:12 PM PDT 24 |
355050147 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3678575180 |
|
|
Aug 15 06:12:30 PM PDT 24 |
Aug 15 06:12:30 PM PDT 24 |
13526617 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.615436676 |
|
|
Aug 15 06:12:08 PM PDT 24 |
Aug 15 06:12:09 PM PDT 24 |
28295335 ps |
| T160 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.918670130 |
|
|
Aug 15 06:12:35 PM PDT 24 |
Aug 15 06:12:37 PM PDT 24 |
208895744 ps |
| T986 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2964424790 |
|
|
Aug 15 06:12:07 PM PDT 24 |
Aug 15 06:12:34 PM PDT 24 |
3831061656 ps |
| T154 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.618687209 |
|
|
Aug 15 06:12:30 PM PDT 24 |
Aug 15 06:12:33 PM PDT 24 |
182050558 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1381749288 |
|
|
Aug 15 06:12:10 PM PDT 24 |
Aug 15 06:12:11 PM PDT 24 |
65766624 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3820755390 |
|
|
Aug 15 06:12:05 PM PDT 24 |
Aug 15 06:12:06 PM PDT 24 |
17547937 ps |
| T161 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2282444049 |
|
|
Aug 15 06:12:16 PM PDT 24 |
Aug 15 06:12:18 PM PDT 24 |
329857997 ps |
| T116 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.61767374 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:45 PM PDT 24 |
7136936235 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2598893589 |
|
|
Aug 15 06:12:34 PM PDT 24 |
Aug 15 06:12:37 PM PDT 24 |
181361330 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4201103867 |
|
|
Aug 15 06:12:30 PM PDT 24 |
Aug 15 06:12:31 PM PDT 24 |
16667485 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1210464828 |
|
|
Aug 15 06:12:02 PM PDT 24 |
Aug 15 06:12:07 PM PDT 24 |
561802594 ps |
| T158 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3810345900 |
|
|
Aug 15 06:12:33 PM PDT 24 |
Aug 15 06:12:40 PM PDT 24 |
7715199222 ps |
| T992 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3319314510 |
|
|
Aug 15 06:12:30 PM PDT 24 |
Aug 15 06:12:34 PM PDT 24 |
322897188 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.378320348 |
|
|
Aug 15 06:12:33 PM PDT 24 |
Aug 15 06:13:28 PM PDT 24 |
13858284664 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1961592074 |
|
|
Aug 15 06:12:34 PM PDT 24 |
Aug 15 06:12:35 PM PDT 24 |
37945198 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2078860490 |
|
|
Aug 15 06:12:18 PM PDT 24 |
Aug 15 06:12:23 PM PDT 24 |
1190743033 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.397020811 |
|
|
Aug 15 06:12:34 PM PDT 24 |
Aug 15 06:13:26 PM PDT 24 |
7337708593 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3661625960 |
|
|
Aug 15 06:12:32 PM PDT 24 |
Aug 15 06:12:36 PM PDT 24 |
346730030 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.695144060 |
|
|
Aug 15 06:12:24 PM PDT 24 |
Aug 15 06:12:26 PM PDT 24 |
26949880 ps |
| T998 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.589339215 |
|
|
Aug 15 06:12:27 PM PDT 24 |
Aug 15 06:13:22 PM PDT 24 |
7393315702 ps |
| T162 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1997935813 |
|
|
Aug 15 06:12:14 PM PDT 24 |
Aug 15 06:12:16 PM PDT 24 |
257091290 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.168889504 |
|
|
Aug 15 06:12:20 PM PDT 24 |
Aug 15 06:12:22 PM PDT 24 |
1252981509 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3024289316 |
|
|
Aug 15 06:12:15 PM PDT 24 |
Aug 15 06:12:16 PM PDT 24 |
14903375 ps |
| T1001 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2004405124 |
|
|
Aug 15 06:12:09 PM PDT 24 |
Aug 15 06:13:01 PM PDT 24 |
7206371038 ps |
| T118 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3778865558 |
|
|
Aug 15 06:12:37 PM PDT 24 |
Aug 15 06:13:06 PM PDT 24 |
8224648031 ps |
| T1002 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2752689099 |
|
|
Aug 15 06:12:41 PM PDT 24 |
Aug 15 06:12:45 PM PDT 24 |
709701292 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2493765079 |
|
|
Aug 15 06:12:22 PM PDT 24 |
Aug 15 06:12:27 PM PDT 24 |
2605268742 ps |