Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16399134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

159100096

1

T2

204337

T3

692

T4

64444

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86444404	1			T2	112736		T3	385		T4	35344
values[0x0]	42900438	1			T2	54031		T3	187		T4	17042
values[0x1]	46154388	1			T2	58072		T3	191		T4	18538

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8343319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167155911

1

T2

214655

T3

723

T4

67692

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	553167	1			T2	826		T3	1		T4	267
valid_sources[0x01]	604541	1			T2	979		T3	2		T4	297
valid_sources[0x02]	588714	1			T2	812		T3	5		T4	298
valid_sources[0x03]	580607	1			T2	905		T3	3		T4	275
valid_sources[0x04]	578892	1			T2	881		T3	4		T4	310
valid_sources[0x05]	543414	1			T2	910		T3	2		T4	280
valid_sources[0x06]	544015	1			T2	907		T3	2		T4	285
valid_sources[0x07]	603664	1			T2	948		T3	4		T4	250
valid_sources[0x08]	566544	1			T2	876		T3	1		T4	302
valid_sources[0x09]	566959	1			T2	919		T3	1		T4	263
valid_sources[0x0a]	748737	1			T2	933		T3	4		T4	288
valid_sources[0x0b]	1485005	1			T2	907		T3	1		T4	306
valid_sources[0x0c]	2007068	1			T2	974		T3	4		T4	302
valid_sources[0x0d]	1712226	1			T2	868		T4	247		T5	325
valid_sources[0x0e]	573979	1			T2	818		T3	4		T4	263
valid_sources[0x0f]	600322	1			T2	965		T3	2		T4	323
valid_sources[0x10]	542427	1			T2	828		T3	1		T4	261
valid_sources[0x11]	553652	1			T2	837		T3	6		T4	276
valid_sources[0x12]	568534	1			T2	827		T3	3		T4	267
valid_sources[0x13]	597784	1			T2	848		T3	1		T4	293
valid_sources[0x14]	555642	1			T2	895		T3	4		T4	303
valid_sources[0x15]	584780	1			T2	948		T3	1		T4	290
valid_sources[0x16]	545526	1			T2	960		T3	3		T4	274
valid_sources[0x17]	550150	1			T2	819		T3	4		T4	283
valid_sources[0x18]	585252	1			T2	869		T3	1		T4	307
valid_sources[0x19]	647580	1			T2	872		T3	4		T4	278
valid_sources[0x1a]	550589	1			T2	905		T3	6		T4	280
valid_sources[0x1b]	2237849	1			T2	897		T3	4		T4	306
valid_sources[0x1c]	577504	1			T2	852		T3	3		T4	265
valid_sources[0x1d]	599614	1			T2	848		T3	6		T4	259
valid_sources[0x1e]	568054	1			T2	904		T3	4		T4	266
valid_sources[0x1f]	591278	1			T2	930		T3	2		T4	219
valid_sources[0x20]	538214	1			T2	816		T3	3		T4	274
valid_sources[0x21]	608108	1			T2	967		T3	1		T4	270
valid_sources[0x22]	619142	1			T2	822		T3	2		T4	284
valid_sources[0x23]	576420	1			T2	861		T3	3		T4	264
valid_sources[0x24]	560898	1			T2	820		T3	5		T4	289
valid_sources[0x25]	641720	1			T2	852		T3	4		T4	260
valid_sources[0x26]	551022	1			T2	849		T3	1		T4	282
valid_sources[0x27]	546662	1			T2	789		T3	2		T4	270
valid_sources[0x28]	558883	1			T2	815		T3	7		T4	279
valid_sources[0x29]	551793	1			T2	940		T3	6		T4	258
valid_sources[0x2a]	564677	1			T2	925		T3	2		T4	294
valid_sources[0x2b]	551224	1			T2	797		T3	2		T4	252
valid_sources[0x2c]	598371	1			T2	861		T3	1		T4	258
valid_sources[0x2d]	743739	1			T2	838		T3	1		T4	284
valid_sources[0x2e]	563794	1			T2	898		T3	2		T4	292
valid_sources[0x2f]	574160	1			T2	910		T3	3		T4	259
valid_sources[0x30]	653489	1			T2	778		T3	3		T4	282
valid_sources[0x31]	571099	1			T2	970		T3	3		T4	281
valid_sources[0x32]	576329	1			T2	796		T3	1		T4	259
valid_sources[0x33]	582815	1			T2	841		T3	2		T4	305
valid_sources[0x34]	554851	1			T2	865		T3	3		T4	256
valid_sources[0x35]	579423	1			T2	771		T3	2		T4	293
valid_sources[0x36]	658050	1			T2	995		T3	4		T4	278
valid_sources[0x37]	551920	1			T2	847		T3	1		T4	292
valid_sources[0x38]	549836	1			T2	879		T3	1		T4	249
valid_sources[0x39]	545156	1			T2	823		T3	3		T4	273
valid_sources[0x3a]	622718	1			T2	938		T3	3		T4	277
valid_sources[0x3b]	551358	1			T2	894		T3	2		T4	276
valid_sources[0x3c]	543143	1			T2	916		T3	2		T4	277
valid_sources[0x3d]	566629	1			T2	898		T4	288		T5	265
valid_sources[0x3e]	1173633	1			T2	814		T3	1		T4	300
valid_sources[0x3f]	558415	1			T2	897		T3	4		T4	316
valid_sources[0x40]	647854	1			T2	954		T3	3		T4	286
valid_sources[0x41]	549924	1			T2	840		T3	2		T4	273
valid_sources[0x42]	588417	1			T2	877		T3	5		T4	280
valid_sources[0x43]	576521	1			T2	972		T3	1		T4	266
valid_sources[0x44]	632041	1			T2	813		T3	2		T4	274
valid_sources[0x45]	597253	1			T2	883		T3	2		T4	262
valid_sources[0x46]	559919	1			T2	958		T3	2		T4	254
valid_sources[0x47]	542451	1			T2	866		T4	259		T5	246
valid_sources[0x48]	564009	1			T2	905		T3	3		T4	255
valid_sources[0x49]	593034	1			T2	871		T3	3		T4	256
valid_sources[0x4a]	554765	1			T2	873		T3	1		T4	278
valid_sources[0x4b]	568457	1			T2	1021		T3	4		T4	256
valid_sources[0x4c]	722379	1			T2	870		T3	2		T4	286
valid_sources[0x4d]	567786	1			T2	833		T3	3		T4	293
valid_sources[0x4e]	588342	1			T2	874		T3	6		T4	286
valid_sources[0x4f]	609320	1			T2	881		T3	8		T4	292
valid_sources[0x50]	597869	1			T2	836		T3	2		T4	308
valid_sources[0x51]	574654	1			T2	806		T4	271		T5	266
valid_sources[0x52]	557718	1			T2	948		T3	5		T4	261
valid_sources[0x53]	736539	1			T2	836		T3	4		T4	264
valid_sources[0x54]	610043	1			T2	875		T3	2		T4	271
valid_sources[0x55]	572103	1			T2	854		T3	4		T4	276
valid_sources[0x56]	572560	1			T2	901		T3	6		T4	281
valid_sources[0x57]	612855	1			T2	896		T3	5		T4	281
valid_sources[0x58]	642691	1			T2	891		T3	3		T4	275
valid_sources[0x59]	568731	1			T2	803		T3	6		T4	296
valid_sources[0x5a]	788305	1			T2	887		T3	2		T4	262
valid_sources[0x5b]	657984	1			T2	894		T3	1		T4	284
valid_sources[0x5c]	567469	1			T2	857		T3	1		T4	254
valid_sources[0x5d]	1206973	1			T2	896		T3	1		T4	279
valid_sources[0x5e]	546563	1			T2	892		T4	273		T5	221
valid_sources[0x5f]	577408	1			T2	906		T3	1		T4	275
valid_sources[0x60]	564655	1			T2	949		T3	3		T4	269
valid_sources[0x61]	600153	1			T2	896		T3	1		T4	273
valid_sources[0x62]	616471	1			T2	957		T3	3		T4	303
valid_sources[0x63]	607125	1			T2	895		T3	5		T4	259
valid_sources[0x64]	597356	1			T2	875		T3	6		T4	289
valid_sources[0x65]	3180413	1			T2	888		T3	6		T4	269
valid_sources[0x66]	596230	1			T2	892		T3	2		T4	290
valid_sources[0x67]	596775	1			T2	878		T3	3		T4	295
valid_sources[0x68]	603535	1			T2	896		T3	8		T4	284
valid_sources[0x69]	2522335	1			T2	814		T3	2		T4	261
valid_sources[0x6a]	601531	1			T2	944		T3	1		T4	250
valid_sources[0x6b]	607123	1			T2	922		T3	3		T4	301
valid_sources[0x6c]	682336	1			T2	892		T3	3		T4	274
valid_sources[0x6d]	556321	1			T2	829		T4	279		T5	329
valid_sources[0x6e]	543940	1			T2	907		T3	5		T4	265
valid_sources[0x6f]	600057	1			T2	848		T3	1		T4	298
valid_sources[0x70]	604552	1			T2	881		T3	4		T4	327
valid_sources[0x71]	543681	1			T2	871		T3	3		T4	247
valid_sources[0x72]	602392	1			T2	900		T3	4		T4	290
valid_sources[0x73]	540520	1			T2	794		T3	3		T4	261
valid_sources[0x74]	618888	1			T2	890		T3	3		T4	251
valid_sources[0x75]	2057545	1			T2	944		T3	6		T4	272
valid_sources[0x76]	577857	1			T2	774		T4	306		T5	316
valid_sources[0x77]	632000	1			T2	905		T3	1		T4	285
valid_sources[0x78]	567202	1			T2	874		T3	2		T4	269
valid_sources[0x79]	568948	1			T2	854		T3	5		T4	294
valid_sources[0x7a]	547414	1			T2	835		T3	4		T4	271
valid_sources[0x7b]	554281	1			T2	799		T3	4		T4	325
valid_sources[0x7c]	647303	1			T2	908		T3	7		T4	298
valid_sources[0x7d]	2888797	1			T2	887		T3	6		T4	251
valid_sources[0x7e]	591596	1			T2	894		T3	5		T4	248
valid_sources[0x7f]	578076	1			T2	974		T3	2		T4	281
valid_sources[0x80]	573086	1			T2	935		T3	4		T4	298

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78203434

1

T2

102490

T3

351

T4

32167

values[0x0]

all_enables

biggest_size

40451934

1

T2

50910

T3

173

T4

16086

values[0x1]

all_enables

biggest_size

40444728

1

T2

50937

T3

168

T4

16191

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43908	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150144

1

T1

5

T2

4

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53725	1			T22	388		T6	25		T7	10
values[0x0]	67966	1			T1	6		T2	5		T4	3
values[0x1]	72361	1			T1	13		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160133

1

T1

8

T2

4

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	632	1			T22	3		T26	3		T27	1
valid_sources[0x01]	697	1			T1	1		T22	1		T75	1
valid_sources[0x02]	688	1			T26	8		T58	2		T144	1
valid_sources[0x03]	686	1			T4	1		T22	26		T26	10
valid_sources[0x04]	762	1			T11	1		T22	3		T26	3
valid_sources[0x05]	797	1			T22	7		T26	5		T27	8
valid_sources[0x06]	802	1			T22	6		T75	1		T26	4
valid_sources[0x07]	942	1			T22	12		T26	3		T27	5
valid_sources[0x08]	982	1			T1	1		T9	1		T22	6
valid_sources[0x09]	780	1			T1	1		T22	17		T26	4
valid_sources[0x0a]	671	1			T11	5		T26	3		T27	1
valid_sources[0x0b]	625	1			T22	4		T28	1		T26	2
valid_sources[0x0c]	817	1			T22	3		T29	3		T26	1
valid_sources[0x0d]	646	1			T22	2		T26	1		T27	2
valid_sources[0x0e]	827	1			T22	17		T26	3		T27	4
valid_sources[0x0f]	717	1			T22	1		T26	1		T61	2
valid_sources[0x10]	681	1			T22	1		T171	5		T26	9
valid_sources[0x11]	577	1			T22	5		T26	9		T106	2
valid_sources[0x12]	1045	1			T5	1		T22	15		T26	2
valid_sources[0x13]	678	1			T22	7		T26	5		T27	1
valid_sources[0x14]	975	1			T26	6		T27	2		T47	1
valid_sources[0x15]	627	1			T22	8		T74	2		T29	1
valid_sources[0x16]	759	1			T29	1		T27	6		T58	2
valid_sources[0x17]	637	1			T23	2		T25	1		T22	6
valid_sources[0x18]	655	1			T22	5		T72	1		T26	2
valid_sources[0x19]	886	1			T22	5		T26	9		T27	5
valid_sources[0x1a]	927	1			T22	6		T29	2		T26	6
valid_sources[0x1b]	724	1			T22	3		T28	4		T26	1
valid_sources[0x1c]	570	1			T22	1		T26	4		T27	2
valid_sources[0x1d]	607	1			T22	3		T26	1		T27	3
valid_sources[0x1e]	680	1			T22	2		T26	3		T27	3
valid_sources[0x1f]	691	1			T26	9		T27	1		T164	2
valid_sources[0x20]	811	1			T11	1		T22	5		T28	1
valid_sources[0x21]	754	1			T22	5		T26	2		T27	4
valid_sources[0x22]	872	1			T63	1		T22	1		T26	2
valid_sources[0x23]	591	1			T2	1		T22	6		T26	3
valid_sources[0x24]	699	1			T26	7		T27	7		T58	5
valid_sources[0x25]	618	1			T22	3		T75	1		T26	6
valid_sources[0x26]	768	1			T23	1		T63	1		T22	5
valid_sources[0x27]	649	1			T22	6		T30	1		T29	2
valid_sources[0x28]	698	1			T2	1		T22	2		T26	2
valid_sources[0x29]	719	1			T22	10		T29	1		T26	3
valid_sources[0x2a]	833	1			T22	1		T26	11		T27	3
valid_sources[0x2b]	714	1			T29	1		T26	3		T27	1
valid_sources[0x2c]	823	1			T22	15		T26	1		T27	5
valid_sources[0x2d]	611	1			T1	1		T4	1		T29	1
valid_sources[0x2e]	812	1			T22	6		T70	2		T26	7
valid_sources[0x2f]	735	1			T22	6		T26	12		T27	2
valid_sources[0x30]	692	1			T22	7		T26	9		T27	2
valid_sources[0x31]	1069	1			T23	1		T45	1		T22	5
valid_sources[0x32]	618	1			T22	3		T29	1		T26	6
valid_sources[0x33]	636	1			T22	1		T26	4		T27	9
valid_sources[0x34]	740	1			T25	1		T22	9		T26	2
valid_sources[0x35]	736	1			T22	4		T71	1		T26	3
valid_sources[0x36]	791	1			T22	6		T27	2		T172	1
valid_sources[0x37]	699	1			T22	6		T27	1		T79	1
valid_sources[0x38]	612	1			T4	1		T22	3		T26	2
valid_sources[0x39]	1350	1			T22	12		T26	6		T27	1
valid_sources[0x3a]	803	1			T25	6		T22	4		T26	6
valid_sources[0x3b]	664	1			T22	5		T29	1		T26	2
valid_sources[0x3c]	664	1			T45	2		T22	9		T26	12
valid_sources[0x3d]	536	1			T22	2		T26	2		T19	1
valid_sources[0x3e]	775	1			T22	12		T26	4		T79	2
valid_sources[0x3f]	661	1			T29	1		T26	5		T27	1
valid_sources[0x40]	1083	1			T22	4		T26	8		T27	6
valid_sources[0x41]	702	1			T22	1		T26	5		T27	3
valid_sources[0x42]	639	1			T22	5		T157	1		T173	1
valid_sources[0x43]	578	1			T22	9		T57	2		T26	6
valid_sources[0x44]	676	1			T45	1		T22	6		T27	13
valid_sources[0x45]	835	1			T22	1		T26	10		T157	1
valid_sources[0x46]	706	1			T45	1		T29	1		T26	3
valid_sources[0x47]	783	1			T22	4		T26	9		T27	8
valid_sources[0x48]	906	1			T26	8		T27	3		T61	20
valid_sources[0x49]	630	1			T1	1		T22	6		T26	1
valid_sources[0x4a]	598	1			T22	6		T26	3		T27	1
valid_sources[0x4b]	607	1			T26	2		T27	2		T61	5
valid_sources[0x4c]	778	1			T1	1		T11	7		T23	3
valid_sources[0x4d]	627	1			T1	1		T25	3		T22	1
valid_sources[0x4e]	1164	1			T22	3		T26	12		T27	2
valid_sources[0x4f]	1028	1			T29	1		T26	4		T27	2
valid_sources[0x50]	781	1			T22	12		T29	1		T26	5
valid_sources[0x51]	609	1			T22	10		T75	1		T26	1
valid_sources[0x52]	614	1			T9	1		T24	3		T22	2
valid_sources[0x53]	663	1			T29	1		T26	1		T27	1
valid_sources[0x54]	665	1			T4	1		T22	5		T27	3
valid_sources[0x55]	788	1			T9	1		T22	13		T29	1
valid_sources[0x56]	779	1			T29	1		T26	1		T27	6
valid_sources[0x57]	886	1			T25	1		T22	3		T26	6
valid_sources[0x58]	837	1			T22	2		T26	10		T27	4
valid_sources[0x59]	643	1			T22	2		T26	6		T27	3
valid_sources[0x5a]	1013	1			T22	7		T26	4		T27	7
valid_sources[0x5b]	717	1			T22	7		T29	2		T26	3
valid_sources[0x5c]	918	1			T1	1		T22	6		T28	3
valid_sources[0x5d]	914	1			T22	5		T26	5		T27	5
valid_sources[0x5e]	817	1			T22	20		T26	7		T27	5
valid_sources[0x5f]	790	1			T22	17		T26	5		T27	1
valid_sources[0x60]	901	1			T11	8		T23	5		T22	1
valid_sources[0x61]	760	1			T22	4		T26	9		T27	7
valid_sources[0x62]	745	1			T4	1		T22	1		T26	4
valid_sources[0x63]	704	1			T22	5		T26	1		T157	2
valid_sources[0x64]	912	1			T1	1		T22	6		T29	1
valid_sources[0x65]	668	1			T22	5		T26	3		T27	1
valid_sources[0x66]	649	1			T22	4		T26	5		T27	8
valid_sources[0x67]	736	1			T29	1		T26	4		T27	6
valid_sources[0x68]	641	1			T10	7		T29	1		T26	3
valid_sources[0x69]	654	1			T22	4		T26	13		T125	3
valid_sources[0x6a]	900	1			T22	5		T27	3		T157	1
valid_sources[0x6b]	955	1			T2	1		T22	7		T26	11
valid_sources[0x6c]	768	1			T22	2		T26	5		T47	1
valid_sources[0x6d]	658	1			T22	13		T26	10		T20	1
valid_sources[0x6e]	780	1			T69	2		T29	1		T26	7
valid_sources[0x6f]	915	1			T22	6		T70	2		T26	4
valid_sources[0x70]	645	1			T23	2		T22	10		T26	6
valid_sources[0x71]	747	1			T1	3		T22	8		T28	3
valid_sources[0x72]	816	1			T22	5		T49	1		T26	7
valid_sources[0x73]	709	1			T22	2		T26	5		T27	7
valid_sources[0x74]	692	1			T22	2		T26	5		T27	2
valid_sources[0x75]	703	1			T22	7		T26	11		T27	8
valid_sources[0x76]	782	1			T29	1		T26	17		T27	3
valid_sources[0x77]	608	1			T1	1		T22	6		T26	10
valid_sources[0x78]	701	1			T22	1		T6	49		T26	10
valid_sources[0x79]	660	1			T22	18		T26	7		T27	4
valid_sources[0x7a]	794	1			T45	1		T22	6		T26	7
valid_sources[0x7b]	597	1			T22	6		T26	2		T27	1
valid_sources[0x7c]	585	1			T1	1		T22	5		T26	6
valid_sources[0x7d]	688	1			T22	5		T29	1		T26	9
valid_sources[0x7e]	579	1			T24	4		T22	1		T26	6
valid_sources[0x7f]	1137	1			T22	4		T27	1		T19	1
valid_sources[0x80]	731	1			T1	1		T22	4		T29	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40552

1

T22

365

T6

14

T7

5

values[0x0]

all_enables

biggest_size

56533

1

T1

3

T2

4

T4

1

values[0x1]

all_enables

biggest_size

53059

1

T1

2

T3

1

T4

1