Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16286020

1

T2

20502

T3

71

T4

6480

full_word

155876311

1

T2

204337

T3

692

T4

64444

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172162051	1			T2	224839		T3	763		T4	70924
auto[TlIntgErrCmd]	87	1			T76	5		T77	4		T78	2
auto[TlIntgErrData]	89	1			T76	2		T77	5		T78	4
auto[TlIntgErrBoth]	104	1			T76	3		T77	1		T78	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83023309

1

T2

112736

T3

385

T4

35344

auto[1]

89139022

1

T2

112103

T3

378

T4

35580

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7968839	1			T2	10246		T3	34		T4	3177
auto[TlIntgErrNone]	partial	auto[1]	8316918	1			T2	10256		T3	37		T4	3303
auto[TlIntgErrNone]	full_word	auto[0]	75054351	1			T2	102490		T3	351		T4	32167
auto[TlIntgErrNone]	full_word	auto[1]	80821943	1			T2	101847		T3	341		T4	32277
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T77	2		T78	1		T146	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T76	4		T77	1		T78	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T76	1		T146	1		T147	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T77	1		T148	2		T149	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T77	1		T78	2		T146	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T76	2		T77	4		T78	2
auto[TlIntgErrData]	full_word	auto[1]	1	1			T150	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T76	1		T78	2		T146	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T76	1		T77	1		T78	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T76	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T146	1		T151	1		T152	1