Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1046725	1			T4	2936		T5	8760		T12	6406
auto[1]	10004029	1			T2	93597		T3	385		T4	690
auto[2]	797180	1			T4	2718		T5	6174		T12	4579
auto[3]	9728505	1			T2	93342		T3	376		T4	435

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13839243	1			T2	155729		T3	631		T4	5239
auto[1]	2034788	1			T2	14949		T3	59		T4	733
auto[2]	2055095	1			T2	14796		T3	66		T4	713
auto[3]	3647313	1			T2	1465		T3	5		T4	94

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8344087

1

T3

761

T4

6779

T12

1

auto[1]

13232352

1

T2

186939

T5

27131

T12

48568

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	449922	1			T4	2413		T24	5		T25	958
auto[0]	auto[0]	auto[1]	46321	1			T4	246		T12	1		T24	1
auto[0]	auto[0]	auto[2]	46611	1			T4	257		T25	111		T45	21
auto[0]	auto[0]	auto[3]	43844	1			T4	20		T25	15		T45	6
auto[0]	auto[1]	auto[0]	2914989	1			T3	325		T4	385		T23	32706
auto[0]	auto[1]	auto[1]	318538	1			T3	26		T4	253		T23	3317
auto[0]	auto[1]	auto[2]	307099	1			T3	32		T4	23		T23	3170
auto[0]	auto[1]	auto[3]	209711	1			T3	2		T4	29		T23	313
auto[0]	auto[2]	auto[0]	331940	1			T4	2278		T25	587		T71	7
auto[0]	auto[2]	auto[1]	36604	1			T4	213		T25	65		T74	736
auto[0]	auto[2]	auto[2]	37704	1			T4	207		T24	2		T25	40
auto[0]	auto[2]	auto[3]	30586	1			T4	20		T24	1		T25	4
auto[0]	auto[3]	auto[0]	2773212	1			T3	306		T4	163		T23	32611
auto[0]	auto[3]	auto[1]	291147	1			T3	33		T4	21		T23	3181
auto[0]	auto[3]	auto[2]	317590	1			T3	34		T4	226		T23	3180
auto[0]	auto[3]	auto[3]	188269	1			T3	3		T4	25		T23	324
auto[1]	auto[0]	auto[0]	15403	1			T5	275		T12	208		T21	1
auto[1]	auto[0]	auto[1]	68981	1			T5	1289		T12	916		T167	2450
auto[1]	auto[0]	auto[2]	68280	1			T5	1314		T12	917		T167	2494
auto[1]	auto[0]	auto[3]	307363	1			T5	5882		T12	4364		T74	3
auto[1]	auto[1]	auto[0]	3674045	1			T2	77972		T5	41		T12	385
auto[1]	auto[1]	auto[1]	636195	1			T2	7141		T5	1275		T12	3158
auto[1]	auto[1]	auto[2]	600576	1			T2	7762		T5	217		T12	1756
auto[1]	auto[1]	auto[3]	1342876	1			T2	722		T5	5713		T12	14405
auto[1]	auto[2]	auto[0]	11328	1			T5	279		T21	1		T168	2
auto[1]	auto[2]	auto[1]	51186	1			T5	1194		T167	2214		T169	1912
auto[1]	auto[2]	auto[2]	54391	1			T5	871		T12	840		T170	1
auto[1]	auto[2]	auto[3]	243441	1			T5	3830		T12	3739		T167	9118
auto[1]	auto[3]	auto[0]	3668404	1			T2	77757		T5	32		T12	184
auto[1]	auto[3]	auto[1]	585816	1			T2	7808		T5	128		T12	787
auto[1]	auto[3]	auto[2]	622844	1			T2	7034		T5	863		T12	3146
auto[1]	auto[3]	auto[3]	1281223	1			T2	743		T5	3928		T12	13763