Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1297908620	217480	0	0
ctrl_regwen_rd_A	1297908620	5193	0	0
exec_rd_A	1297908620	4747	0	0
exec_regwen_rd_A	1297908620	5332	0	0
readback_rd_A	1297908620	3747	0	0
readback_regwen_rd_A	1297908620	3028	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1297908620	217480	0	0
T6	695519	0	0	0
T22	34079	1424	0	0
T26	0	2200	0	0
T27	0	784	0	0
T30	33796	0	0	0
T49	523611	0	0	0
T57	81234	0	0	0
T61	0	15266	0	0
T64	74464	0	0	0
T69	77786	0	0	0
T70	232729	0	0	0
T71	75974	0	0	0
T80	75498	0	0	0
T84	0	3700	0	0
T85	0	1472	0	0
T86	0	3076	0	0
T87	0	2093	0	0
T88	0	5713	0	0
T89	0	4195	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1297908620	5193	0	0
T6	695519	0	0	0
T22	34079	112	0	0
T26	0	136	0	0
T27	0	79	0	0
T30	33796	0	0	0
T49	523611	0	0	0
T57	81234	0	0	0
T64	74464	0	0	0
T69	77786	0	0	0
T70	232729	0	0	0
T71	75974	0	0	0
T80	75498	0	0	0
T86	0	147	0	0
T87	0	149	0	0
T139	0	202	0	0
T140	0	509	0	0
T141	0	263	0	0
T142	0	79	0	0
T143	0	657	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1297908620	4747	0	0
T6	695519	0	0	0
T22	34079	143	0	0
T26	0	102	0	0
T27	0	60	0	0
T30	33796	0	0	0
T49	523611	0	0	0
T57	81234	0	0	0
T64	74464	0	0	0
T69	77786	0	0	0
T70	232729	0	0	0
T71	75974	0	0	0
T80	75498	0	0	0
T86	0	129	0	0
T87	0	174	0	0
T139	0	201	0	0
T140	0	455	0	0
T141	0	265	0	0
T142	0	122	0	0
T143	0	548	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1297908620	5332	0	0
T6	695519	0	0	0
T22	34079	181	0	0
T26	0	75	0	0
T27	0	55	0	0
T30	33796	0	0	0
T49	523611	0	0	0
T57	81234	0	0	0
T64	74464	0	0	0
T69	77786	0	0	0
T70	232729	0	0	0
T71	75974	0	0	0
T80	75498	0	0	0
T86	0	102	0	0
T87	0	197	0	0
T139	0	256	0	0
T140	0	589	0	0
T141	0	276	0	0
T142	0	95	0	0
T143	0	534	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1297908620	3747	0	0
T6	695519	0	0	0
T22	34079	149	0	0
T26	0	125	0	0
T27	0	57	0	0
T30	33796	0	0	0
T49	523611	0	0	0
T57	81234	0	0	0
T64	74464	0	0	0
T69	77786	0	0	0
T70	232729	0	0	0
T71	75974	0	0	0
T80	75498	0	0	0
T86	0	98	0	0
T87	0	256	0	0
T139	0	184	0	0
T140	0	443	0	0
T141	0	319	0	0
T142	0	112	0	0
T143	0	498	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1297908620	3028	0	0
T6	695519	0	0	0
T22	34079	143	0	0
T26	0	40	0	0
T27	0	22	0	0
T30	33796	0	0	0
T49	523611	0	0	0
T57	81234	0	0	0
T64	74464	0	0	0
T69	77786	0	0	0
T70	232729	0	0	0
T71	75974	0	0	0
T80	75498	0	0	0
T86	0	70	0	0
T87	0	121	0	0
T139	0	137	0	0
T140	0	283	0	0
T141	0	319	0	0
T142	0	117	0	0
T143	0	407	0	0