| T797 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3124705727 |
|
|
Aug 16 05:57:59 PM PDT 24 |
Aug 16 05:58:08 PM PDT 24 |
831666034 ps |
| T798 |
/workspace/coverage/default/38.sram_ctrl_alert_test.1601504673 |
|
|
Aug 16 05:58:41 PM PDT 24 |
Aug 16 05:58:42 PM PDT 24 |
40760313 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2600117635 |
|
|
Aug 16 05:57:37 PM PDT 24 |
Aug 16 05:59:53 PM PDT 24 |
1677421951 ps |
| T800 |
/workspace/coverage/default/26.sram_ctrl_stress_all.2175712219 |
|
|
Aug 16 05:58:04 PM PDT 24 |
Aug 16 07:07:23 PM PDT 24 |
531258659318 ps |
| T33 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1466889073 |
|
|
Aug 16 05:56:47 PM PDT 24 |
Aug 16 05:56:51 PM PDT 24 |
468499504 ps |
| T801 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.3373889370 |
|
|
Aug 16 05:59:15 PM PDT 24 |
Aug 16 05:59:22 PM PDT 24 |
1124781641 ps |
| T802 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1775795185 |
|
|
Aug 16 05:59:00 PM PDT 24 |
Aug 16 06:00:12 PM PDT 24 |
11520525861 ps |
| T803 |
/workspace/coverage/default/43.sram_ctrl_alert_test.1609062464 |
|
|
Aug 16 05:59:12 PM PDT 24 |
Aug 16 05:59:13 PM PDT 24 |
43936156 ps |
| T804 |
/workspace/coverage/default/27.sram_ctrl_regwen.1809029169 |
|
|
Aug 16 05:57:43 PM PDT 24 |
Aug 16 06:07:33 PM PDT 24 |
12910155823 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_smoke.3858565194 |
|
|
Aug 16 05:57:37 PM PDT 24 |
Aug 16 05:58:05 PM PDT 24 |
789653884 ps |
| T806 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1194211197 |
|
|
Aug 16 05:59:14 PM PDT 24 |
Aug 16 06:06:05 PM PDT 24 |
6808777008 ps |
| T807 |
/workspace/coverage/default/14.sram_ctrl_smoke.2625199947 |
|
|
Aug 16 05:58:00 PM PDT 24 |
Aug 16 05:58:18 PM PDT 24 |
4428214759 ps |
| T808 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.12888019 |
|
|
Aug 16 05:58:42 PM PDT 24 |
Aug 16 06:02:58 PM PDT 24 |
5470974034 ps |
| T809 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2992589855 |
|
|
Aug 16 05:57:33 PM PDT 24 |
Aug 16 06:22:16 PM PDT 24 |
56703624097 ps |
| T810 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3427096458 |
|
|
Aug 16 05:58:29 PM PDT 24 |
Aug 16 06:00:00 PM PDT 24 |
13972236255 ps |
| T811 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1860544110 |
|
|
Aug 16 05:57:57 PM PDT 24 |
Aug 16 05:59:07 PM PDT 24 |
10949079248 ps |
| T812 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2776526908 |
|
|
Aug 16 05:59:09 PM PDT 24 |
Aug 16 05:59:37 PM PDT 24 |
745133539 ps |
| T813 |
/workspace/coverage/default/19.sram_ctrl_stress_all.565997772 |
|
|
Aug 16 05:57:45 PM PDT 24 |
Aug 16 06:51:28 PM PDT 24 |
180221422094 ps |
| T814 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1912061979 |
|
|
Aug 16 05:57:14 PM PDT 24 |
Aug 16 05:58:10 PM PDT 24 |
1530757849 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2929971989 |
|
|
Aug 16 05:57:32 PM PDT 24 |
Aug 16 05:57:32 PM PDT 24 |
36661738 ps |
| T816 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2107129806 |
|
|
Aug 16 05:57:54 PM PDT 24 |
Aug 16 06:05:24 PM PDT 24 |
21449488687 ps |
| T817 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1899968569 |
|
|
Aug 16 05:57:50 PM PDT 24 |
Aug 16 05:57:53 PM PDT 24 |
359353111 ps |
| T818 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3693630504 |
|
|
Aug 16 05:56:32 PM PDT 24 |
Aug 16 06:00:43 PM PDT 24 |
13378991945 ps |
| T819 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3535831463 |
|
|
Aug 16 05:58:49 PM PDT 24 |
Aug 16 06:01:05 PM PDT 24 |
793903274 ps |
| T820 |
/workspace/coverage/default/49.sram_ctrl_regwen.277524248 |
|
|
Aug 16 05:59:49 PM PDT 24 |
Aug 16 06:08:49 PM PDT 24 |
39353333909 ps |
| T821 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1157990994 |
|
|
Aug 16 05:57:59 PM PDT 24 |
Aug 16 05:58:18 PM PDT 24 |
12991479817 ps |
| T822 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.4178766685 |
|
|
Aug 16 05:59:19 PM PDT 24 |
Aug 16 05:59:26 PM PDT 24 |
2796435736 ps |
| T823 |
/workspace/coverage/default/24.sram_ctrl_bijection.3832765646 |
|
|
Aug 16 05:58:03 PM PDT 24 |
Aug 16 06:15:27 PM PDT 24 |
83182423899 ps |
| T824 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2988175435 |
|
|
Aug 16 05:58:06 PM PDT 24 |
Aug 16 06:00:33 PM PDT 24 |
781983892 ps |
| T825 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1953700629 |
|
|
Aug 16 05:58:53 PM PDT 24 |
Aug 16 06:31:20 PM PDT 24 |
142693506664 ps |
| T826 |
/workspace/coverage/default/17.sram_ctrl_executable.3447123940 |
|
|
Aug 16 05:57:19 PM PDT 24 |
Aug 16 06:16:57 PM PDT 24 |
84714446031 ps |
| T827 |
/workspace/coverage/default/29.sram_ctrl_executable.3533564572 |
|
|
Aug 16 05:58:14 PM PDT 24 |
Aug 16 06:06:22 PM PDT 24 |
14888054602 ps |
| T828 |
/workspace/coverage/default/45.sram_ctrl_partial_access.4023598210 |
|
|
Aug 16 05:59:09 PM PDT 24 |
Aug 16 05:59:24 PM PDT 24 |
3598455227 ps |
| T829 |
/workspace/coverage/default/48.sram_ctrl_smoke.2748335729 |
|
|
Aug 16 05:59:41 PM PDT 24 |
Aug 16 05:59:48 PM PDT 24 |
806821832 ps |
| T830 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3656486604 |
|
|
Aug 16 05:57:34 PM PDT 24 |
Aug 16 05:57:57 PM PDT 24 |
737871228 ps |
| T831 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.347226786 |
|
|
Aug 16 05:58:30 PM PDT 24 |
Aug 16 06:01:34 PM PDT 24 |
1634328476 ps |
| T832 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3021190194 |
|
|
Aug 16 05:56:42 PM PDT 24 |
Aug 16 05:56:42 PM PDT 24 |
95045024 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_bijection.1551090414 |
|
|
Aug 16 05:57:52 PM PDT 24 |
Aug 16 06:10:33 PM PDT 24 |
11178931080 ps |
| T834 |
/workspace/coverage/default/39.sram_ctrl_bijection.318857836 |
|
|
Aug 16 05:58:51 PM PDT 24 |
Aug 16 06:16:59 PM PDT 24 |
47141622059 ps |
| T835 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3387024071 |
|
|
Aug 16 05:57:37 PM PDT 24 |
Aug 16 06:00:54 PM PDT 24 |
2784129577 ps |
| T836 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.701155305 |
|
|
Aug 16 05:57:58 PM PDT 24 |
Aug 16 05:58:45 PM PDT 24 |
11957395563 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1074628924 |
|
|
Aug 16 05:58:12 PM PDT 24 |
Aug 16 05:58:20 PM PDT 24 |
989755262 ps |
| T838 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2298426510 |
|
|
Aug 16 05:57:13 PM PDT 24 |
Aug 16 05:57:24 PM PDT 24 |
3581793520 ps |
| T839 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1643923842 |
|
|
Aug 16 05:57:14 PM PDT 24 |
Aug 16 05:57:18 PM PDT 24 |
679208734 ps |
| T840 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1285486549 |
|
|
Aug 16 05:57:14 PM PDT 24 |
Aug 16 06:27:17 PM PDT 24 |
52081130067 ps |
| T841 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3288188679 |
|
|
Aug 16 05:57:13 PM PDT 24 |
Aug 16 06:15:59 PM PDT 24 |
13357994488 ps |
| T842 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2755774140 |
|
|
Aug 16 05:59:29 PM PDT 24 |
Aug 16 06:00:41 PM PDT 24 |
41943999691 ps |
| T843 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.801151011 |
|
|
Aug 16 05:59:41 PM PDT 24 |
Aug 16 06:00:29 PM PDT 24 |
3034009013 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.2438901216 |
|
|
Aug 16 05:58:01 PM PDT 24 |
Aug 16 05:58:13 PM PDT 24 |
1431298619 ps |
| T845 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2428383578 |
|
|
Aug 16 05:57:12 PM PDT 24 |
Aug 16 06:26:07 PM PDT 24 |
56130390328 ps |
| T846 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.4097486276 |
|
|
Aug 16 05:58:58 PM PDT 24 |
Aug 16 06:01:34 PM PDT 24 |
5684818576 ps |
| T847 |
/workspace/coverage/default/39.sram_ctrl_executable.1762148898 |
|
|
Aug 16 05:58:59 PM PDT 24 |
Aug 16 06:05:30 PM PDT 24 |
16762581646 ps |
| T848 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1651918220 |
|
|
Aug 16 05:58:18 PM PDT 24 |
Aug 16 06:01:02 PM PDT 24 |
5531742803 ps |
| T849 |
/workspace/coverage/default/46.sram_ctrl_bijection.3728244557 |
|
|
Aug 16 05:59:21 PM PDT 24 |
Aug 16 06:26:50 PM PDT 24 |
69242487476 ps |
| T850 |
/workspace/coverage/default/19.sram_ctrl_regwen.150402544 |
|
|
Aug 16 05:57:46 PM PDT 24 |
Aug 16 06:11:11 PM PDT 24 |
11305480435 ps |
| T851 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2967097220 |
|
|
Aug 16 05:59:11 PM PDT 24 |
Aug 16 05:59:22 PM PDT 24 |
1466611837 ps |
| T852 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3156331996 |
|
|
Aug 16 05:57:57 PM PDT 24 |
Aug 16 05:59:46 PM PDT 24 |
8433026461 ps |
| T853 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3325311015 |
|
|
Aug 16 05:56:46 PM PDT 24 |
Aug 16 05:57:58 PM PDT 24 |
12399968589 ps |
| T854 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3542676115 |
|
|
Aug 16 05:57:42 PM PDT 24 |
Aug 16 06:01:38 PM PDT 24 |
7687420805 ps |
| T855 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2488141756 |
|
|
Aug 16 05:57:13 PM PDT 24 |
Aug 16 06:01:30 PM PDT 24 |
3745864902 ps |
| T856 |
/workspace/coverage/default/20.sram_ctrl_bijection.2211904317 |
|
|
Aug 16 05:58:01 PM PDT 24 |
Aug 16 06:14:48 PM PDT 24 |
64171927121 ps |
| T857 |
/workspace/coverage/default/46.sram_ctrl_alert_test.77745821 |
|
|
Aug 16 05:59:27 PM PDT 24 |
Aug 16 05:59:28 PM PDT 24 |
47458180 ps |
| T858 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.4087308761 |
|
|
Aug 16 05:58:10 PM PDT 24 |
Aug 16 06:00:32 PM PDT 24 |
803228112 ps |
| T859 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3871440888 |
|
|
Aug 16 05:57:22 PM PDT 24 |
Aug 16 06:14:57 PM PDT 24 |
42166163626 ps |
| T860 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.1299936742 |
|
|
Aug 16 05:58:12 PM PDT 24 |
Aug 16 05:58:16 PM PDT 24 |
355978328 ps |
| T861 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3863341447 |
|
|
Aug 16 05:57:51 PM PDT 24 |
Aug 16 05:58:55 PM PDT 24 |
99947253785 ps |
| T862 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.717918995 |
|
|
Aug 16 05:57:51 PM PDT 24 |
Aug 16 05:58:59 PM PDT 24 |
85494053401 ps |
| T863 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2909308471 |
|
|
Aug 16 05:59:16 PM PDT 24 |
Aug 16 06:02:49 PM PDT 24 |
7022358766 ps |
| T864 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3217714415 |
|
|
Aug 16 05:56:40 PM PDT 24 |
Aug 16 05:57:45 PM PDT 24 |
3856112613 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3657365957 |
|
|
Aug 16 05:57:10 PM PDT 24 |
Aug 16 05:59:37 PM PDT 24 |
9977866595 ps |
| T866 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2586869864 |
|
|
Aug 16 05:58:09 PM PDT 24 |
Aug 16 05:58:12 PM PDT 24 |
2584917128 ps |
| T867 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3229171248 |
|
|
Aug 16 05:57:54 PM PDT 24 |
Aug 16 06:02:12 PM PDT 24 |
10683008976 ps |
| T868 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1731361042 |
|
|
Aug 16 05:57:39 PM PDT 24 |
Aug 16 06:03:12 PM PDT 24 |
4369924752 ps |
| T869 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2325517608 |
|
|
Aug 16 05:56:44 PM PDT 24 |
Aug 16 05:59:04 PM PDT 24 |
3047233612 ps |
| T870 |
/workspace/coverage/default/32.sram_ctrl_alert_test.814613578 |
|
|
Aug 16 05:58:12 PM PDT 24 |
Aug 16 05:58:12 PM PDT 24 |
21826649 ps |
| T871 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2829000730 |
|
|
Aug 16 05:56:38 PM PDT 24 |
Aug 16 05:59:20 PM PDT 24 |
884287817 ps |
| T872 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1741865139 |
|
|
Aug 16 05:57:13 PM PDT 24 |
Aug 16 06:18:04 PM PDT 24 |
7534552431 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3983263139 |
|
|
Aug 16 05:56:58 PM PDT 24 |
Aug 16 05:57:20 PM PDT 24 |
938253076 ps |
| T874 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.720389257 |
|
|
Aug 16 05:57:12 PM PDT 24 |
Aug 16 05:58:51 PM PDT 24 |
6247742527 ps |
| T875 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1351750234 |
|
|
Aug 16 05:58:17 PM PDT 24 |
Aug 16 06:48:48 PM PDT 24 |
48435110430 ps |
| T876 |
/workspace/coverage/default/11.sram_ctrl_alert_test.778146299 |
|
|
Aug 16 05:56:59 PM PDT 24 |
Aug 16 05:57:00 PM PDT 24 |
15095410 ps |
| T877 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2809930145 |
|
|
Aug 16 05:57:40 PM PDT 24 |
Aug 16 06:33:14 PM PDT 24 |
80919621556 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_smoke.1925362174 |
|
|
Aug 16 05:56:48 PM PDT 24 |
Aug 16 05:58:03 PM PDT 24 |
776421554 ps |
| T879 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1618766301 |
|
|
Aug 16 05:57:31 PM PDT 24 |
Aug 16 06:00:06 PM PDT 24 |
5483822246 ps |
| T880 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1567399103 |
|
|
Aug 16 05:59:57 PM PDT 24 |
Aug 16 06:02:09 PM PDT 24 |
2517530122 ps |
| T881 |
/workspace/coverage/default/1.sram_ctrl_regwen.3524627763 |
|
|
Aug 16 05:57:07 PM PDT 24 |
Aug 16 06:05:43 PM PDT 24 |
39699481817 ps |
| T882 |
/workspace/coverage/default/48.sram_ctrl_executable.1248074260 |
|
|
Aug 16 05:59:39 PM PDT 24 |
Aug 16 06:11:08 PM PDT 24 |
51128341891 ps |
| T883 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2503897189 |
|
|
Aug 16 05:59:04 PM PDT 24 |
Aug 16 06:00:13 PM PDT 24 |
1392717071 ps |
| T884 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1981714751 |
|
|
Aug 16 05:58:38 PM PDT 24 |
Aug 16 06:20:37 PM PDT 24 |
18426919862 ps |
| T885 |
/workspace/coverage/default/41.sram_ctrl_bijection.2804370138 |
|
|
Aug 16 05:59:04 PM PDT 24 |
Aug 16 06:09:49 PM PDT 24 |
19430592165 ps |
| T886 |
/workspace/coverage/default/12.sram_ctrl_executable.1054861919 |
|
|
Aug 16 05:57:37 PM PDT 24 |
Aug 16 06:07:01 PM PDT 24 |
24370106653 ps |
| T887 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2411008963 |
|
|
Aug 16 05:57:28 PM PDT 24 |
Aug 16 06:00:04 PM PDT 24 |
228627567511 ps |
| T888 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2497270266 |
|
|
Aug 16 05:57:13 PM PDT 24 |
Aug 16 05:58:23 PM PDT 24 |
1430434918 ps |
| T889 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2242806460 |
|
|
Aug 16 05:56:57 PM PDT 24 |
Aug 16 06:02:25 PM PDT 24 |
55343093341 ps |
| T890 |
/workspace/coverage/default/38.sram_ctrl_executable.3754965297 |
|
|
Aug 16 05:58:48 PM PDT 24 |
Aug 16 06:19:37 PM PDT 24 |
45431424825 ps |
| T891 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.347076606 |
|
|
Aug 16 05:56:58 PM PDT 24 |
Aug 16 05:57:13 PM PDT 24 |
715448205 ps |
| T892 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2035831573 |
|
|
Aug 16 05:57:22 PM PDT 24 |
Aug 16 05:57:26 PM PDT 24 |
787200682 ps |
| T893 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2122418770 |
|
|
Aug 16 05:57:53 PM PDT 24 |
Aug 16 06:02:18 PM PDT 24 |
9240170104 ps |
| T894 |
/workspace/coverage/default/36.sram_ctrl_smoke.2677861464 |
|
|
Aug 16 05:58:45 PM PDT 24 |
Aug 16 05:59:03 PM PDT 24 |
5006406320 ps |
| T895 |
/workspace/coverage/default/23.sram_ctrl_alert_test.721894055 |
|
|
Aug 16 05:58:01 PM PDT 24 |
Aug 16 05:58:02 PM PDT 24 |
44245131 ps |
| T896 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1637694857 |
|
|
Aug 16 05:57:22 PM PDT 24 |
Aug 16 05:59:28 PM PDT 24 |
821624965 ps |
| T897 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.2270797087 |
|
|
Aug 16 05:57:30 PM PDT 24 |
Aug 16 06:00:16 PM PDT 24 |
8965200132 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.712825922 |
|
|
Aug 16 05:56:58 PM PDT 24 |
Aug 16 05:59:50 PM PDT 24 |
23242007695 ps |
| T899 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.929088365 |
|
|
Aug 16 05:58:48 PM PDT 24 |
Aug 16 06:03:01 PM PDT 24 |
41359421654 ps |
| T900 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.4276133465 |
|
|
Aug 16 05:57:42 PM PDT 24 |
Aug 16 06:03:04 PM PDT 24 |
4933193157 ps |
| T901 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1530241945 |
|
|
Aug 16 05:59:43 PM PDT 24 |
Aug 16 06:17:20 PM PDT 24 |
22275074696 ps |
| T902 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1970635848 |
|
|
Aug 16 05:59:40 PM PDT 24 |
Aug 16 06:00:33 PM PDT 24 |
11399805002 ps |
| T903 |
/workspace/coverage/default/37.sram_ctrl_smoke.1586271698 |
|
|
Aug 16 05:58:34 PM PDT 24 |
Aug 16 05:58:43 PM PDT 24 |
848062191 ps |
| T904 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1795964421 |
|
|
Aug 16 05:56:46 PM PDT 24 |
Aug 16 05:56:47 PM PDT 24 |
16289287 ps |
| T905 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3837816031 |
|
|
Aug 16 05:57:21 PM PDT 24 |
Aug 16 05:59:57 PM PDT 24 |
42535480105 ps |
| T906 |
/workspace/coverage/default/37.sram_ctrl_executable.2868465617 |
|
|
Aug 16 05:58:39 PM PDT 24 |
Aug 16 06:01:52 PM PDT 24 |
12497644389 ps |
| T907 |
/workspace/coverage/default/35.sram_ctrl_regwen.972750737 |
|
|
Aug 16 05:58:42 PM PDT 24 |
Aug 16 06:18:36 PM PDT 24 |
24899978426 ps |
| T908 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1970540044 |
|
|
Aug 16 05:56:56 PM PDT 24 |
Aug 16 05:57:08 PM PDT 24 |
1925148084 ps |
| T909 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2903559576 |
|
|
Aug 16 05:58:34 PM PDT 24 |
Aug 16 06:06:11 PM PDT 24 |
239608141412 ps |
| T910 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.2626840499 |
|
|
Aug 16 05:58:31 PM PDT 24 |
Aug 16 06:27:09 PM PDT 24 |
38242015268 ps |
| T911 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.371311822 |
|
|
Aug 16 05:58:03 PM PDT 24 |
Aug 16 06:00:59 PM PDT 24 |
11907045032 ps |
| T912 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.4194132313 |
|
|
Aug 16 05:58:30 PM PDT 24 |
Aug 16 05:58:33 PM PDT 24 |
1341086523 ps |
| T913 |
/workspace/coverage/default/2.sram_ctrl_regwen.1865938575 |
|
|
Aug 16 05:57:10 PM PDT 24 |
Aug 16 06:12:52 PM PDT 24 |
31459288898 ps |
| T914 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1469917260 |
|
|
Aug 16 05:57:12 PM PDT 24 |
Aug 16 05:58:05 PM PDT 24 |
1441000398 ps |
| T915 |
/workspace/coverage/default/34.sram_ctrl_alert_test.4126811298 |
|
|
Aug 16 05:58:18 PM PDT 24 |
Aug 16 05:58:19 PM PDT 24 |
48491453 ps |
| T916 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.874617557 |
|
|
Aug 16 05:57:55 PM PDT 24 |
Aug 16 06:02:36 PM PDT 24 |
8047059472 ps |
| T917 |
/workspace/coverage/default/0.sram_ctrl_regwen.887811343 |
|
|
Aug 16 05:56:34 PM PDT 24 |
Aug 16 06:08:11 PM PDT 24 |
20791840894 ps |
| T918 |
/workspace/coverage/default/33.sram_ctrl_bijection.4216743335 |
|
|
Aug 16 05:58:38 PM PDT 24 |
Aug 16 06:26:07 PM PDT 24 |
345923953413 ps |
| T919 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1513885632 |
|
|
Aug 16 05:56:31 PM PDT 24 |
Aug 16 05:56:46 PM PDT 24 |
1048136980 ps |
| T920 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.542468136 |
|
|
Aug 16 05:59:05 PM PDT 24 |
Aug 16 06:03:53 PM PDT 24 |
4858246695 ps |
| T921 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2875768515 |
|
|
Aug 16 05:57:10 PM PDT 24 |
Aug 16 05:58:11 PM PDT 24 |
1036715475 ps |
| T922 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3276744537 |
|
|
Aug 16 05:57:59 PM PDT 24 |
Aug 16 05:58:14 PM PDT 24 |
914790612 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3519947472 |
|
|
Aug 16 05:57:36 PM PDT 24 |
Aug 16 05:59:53 PM PDT 24 |
15163088688 ps |
| T924 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3965513142 |
|
|
Aug 16 05:56:41 PM PDT 24 |
Aug 16 05:56:42 PM PDT 24 |
12520563 ps |
| T925 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2133450364 |
|
|
Aug 16 05:58:11 PM PDT 24 |
Aug 16 05:58:12 PM PDT 24 |
31675955 ps |
| T926 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.513817637 |
|
|
Aug 16 05:57:40 PM PDT 24 |
Aug 16 06:00:29 PM PDT 24 |
28893423817 ps |
| T927 |
/workspace/coverage/default/33.sram_ctrl_executable.679920555 |
|
|
Aug 16 05:58:10 PM PDT 24 |
Aug 16 06:18:04 PM PDT 24 |
70880618781 ps |
| T928 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2818069758 |
|
|
Aug 16 05:56:40 PM PDT 24 |
Aug 16 05:56:47 PM PDT 24 |
669052162 ps |
| T929 |
/workspace/coverage/default/13.sram_ctrl_smoke.4210195832 |
|
|
Aug 16 05:57:10 PM PDT 24 |
Aug 16 05:57:24 PM PDT 24 |
777989990 ps |
| T930 |
/workspace/coverage/default/34.sram_ctrl_executable.2356096597 |
|
|
Aug 16 05:58:15 PM PDT 24 |
Aug 16 06:04:40 PM PDT 24 |
29220464781 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3399339750 |
|
|
Aug 16 05:57:15 PM PDT 24 |
Aug 16 05:58:59 PM PDT 24 |
14131398130 ps |
| T932 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2896485488 |
|
|
Aug 16 05:59:01 PM PDT 24 |
Aug 16 06:34:53 PM PDT 24 |
55057740753 ps |
| T933 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1436028169 |
|
|
Aug 16 05:57:57 PM PDT 24 |
Aug 16 05:58:31 PM PDT 24 |
9736893943 ps |
| T34 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3379839781 |
|
|
Aug 16 05:57:11 PM PDT 24 |
Aug 16 05:57:14 PM PDT 24 |
184847909 ps |
| T934 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3018584128 |
|
|
Aug 16 05:58:53 PM PDT 24 |
Aug 16 05:59:08 PM PDT 24 |
1661427365 ps |
| T935 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.4100425057 |
|
|
Aug 16 05:56:54 PM PDT 24 |
Aug 16 05:56:58 PM PDT 24 |
348083491 ps |
| T936 |
/workspace/coverage/default/6.sram_ctrl_smoke.2853183292 |
|
|
Aug 16 05:56:50 PM PDT 24 |
Aug 16 05:57:04 PM PDT 24 |
811852577 ps |
| T937 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3430835594 |
|
|
Aug 16 05:58:19 PM PDT 24 |
Aug 16 06:05:20 PM PDT 24 |
63116679336 ps |
| T938 |
/workspace/coverage/default/26.sram_ctrl_regwen.1528797928 |
|
|
Aug 16 05:57:42 PM PDT 24 |
Aug 16 06:08:09 PM PDT 24 |
5440416433 ps |
| T939 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.310933714 |
|
|
Aug 16 05:57:32 PM PDT 24 |
Aug 16 06:00:08 PM PDT 24 |
2743248822 ps |
| T940 |
/workspace/coverage/default/44.sram_ctrl_smoke.505825700 |
|
|
Aug 16 05:59:12 PM PDT 24 |
Aug 16 06:01:28 PM PDT 24 |
4740268386 ps |
| T941 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1371043171 |
|
|
Aug 16 05:59:41 PM PDT 24 |
Aug 16 05:59:42 PM PDT 24 |
28420897 ps |
| T942 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1914008844 |
|
|
Aug 16 05:58:55 PM PDT 24 |
Aug 16 06:16:33 PM PDT 24 |
68619415706 ps |
| T943 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3048010608 |
|
|
Aug 16 05:58:04 PM PDT 24 |
Aug 16 06:03:21 PM PDT 24 |
24993933614 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1371892443 |
|
|
Aug 16 05:49:14 PM PDT 24 |
Aug 16 05:49:15 PM PDT 24 |
115177471 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1385047548 |
|
|
Aug 16 05:49:17 PM PDT 24 |
Aug 16 05:49:21 PM PDT 24 |
151659265 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.737968490 |
|
|
Aug 16 05:49:45 PM PDT 24 |
Aug 16 05:49:46 PM PDT 24 |
62266201 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1499264747 |
|
|
Aug 16 05:49:16 PM PDT 24 |
Aug 16 05:49:18 PM PDT 24 |
268993578 ps |
| T120 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.769519861 |
|
|
Aug 16 05:51:06 PM PDT 24 |
Aug 16 05:52:00 PM PDT 24 |
41575500727 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1433064448 |
|
|
Aug 16 05:51:07 PM PDT 24 |
Aug 16 05:52:03 PM PDT 24 |
30657725189 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3909360119 |
|
|
Aug 16 05:49:34 PM PDT 24 |
Aug 16 05:50:27 PM PDT 24 |
28157274695 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4264649026 |
|
|
Aug 16 05:49:16 PM PDT 24 |
Aug 16 05:49:17 PM PDT 24 |
14651852 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2747627208 |
|
|
Aug 16 05:49:46 PM PDT 24 |
Aug 16 05:49:49 PM PDT 24 |
365652417 ps |
| T137 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2234818110 |
|
|
Aug 16 05:50:23 PM PDT 24 |
Aug 16 05:50:24 PM PDT 24 |
15756306 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3142848496 |
|
|
Aug 16 05:50:23 PM PDT 24 |
Aug 16 05:50:24 PM PDT 24 |
50357952 ps |
| T121 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3491457706 |
|
|
Aug 16 05:49:13 PM PDT 24 |
Aug 16 05:49:14 PM PDT 24 |
17331040 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3052977227 |
|
|
Aug 16 05:49:02 PM PDT 24 |
Aug 16 05:49:04 PM PDT 24 |
93425662 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1132342580 |
|
|
Aug 16 05:49:13 PM PDT 24 |
Aug 16 05:49:15 PM PDT 24 |
141988412 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3262999928 |
|
|
Aug 16 05:49:23 PM PDT 24 |
Aug 16 05:49:24 PM PDT 24 |
28414191 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.447971032 |
|
|
Aug 16 05:49:19 PM PDT 24 |
Aug 16 05:49:48 PM PDT 24 |
7875699173 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3551896538 |
|
|
Aug 16 05:49:37 PM PDT 24 |
Aug 16 05:49:38 PM PDT 24 |
41134721 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2550654818 |
|
|
Aug 16 05:49:49 PM PDT 24 |
Aug 16 05:49:52 PM PDT 24 |
682638958 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.686061776 |
|
|
Aug 16 05:51:51 PM PDT 24 |
Aug 16 05:52:42 PM PDT 24 |
7072031242 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2656577255 |
|
|
Aug 16 05:49:09 PM PDT 24 |
Aug 16 05:49:11 PM PDT 24 |
114905349 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3280376816 |
|
|
Aug 16 05:49:14 PM PDT 24 |
Aug 16 05:49:15 PM PDT 24 |
70348825 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3202522801 |
|
|
Aug 16 05:50:03 PM PDT 24 |
Aug 16 05:50:56 PM PDT 24 |
14236628731 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.106017402 |
|
|
Aug 16 05:49:07 PM PDT 24 |
Aug 16 05:49:08 PM PDT 24 |
33784680 ps |
| T96 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.291178180 |
|
|
Aug 16 05:49:14 PM PDT 24 |
Aug 16 05:50:12 PM PDT 24 |
35447924758 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1298760155 |
|
|
Aug 16 05:51:45 PM PDT 24 |
Aug 16 05:51:49 PM PDT 24 |
421715112 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3097856616 |
|
|
Aug 16 05:49:15 PM PDT 24 |
Aug 16 05:49:17 PM PDT 24 |
26097433 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2720876528 |
|
|
Aug 16 05:50:07 PM PDT 24 |
Aug 16 05:50:10 PM PDT 24 |
369415849 ps |
| T97 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.583698259 |
|
|
Aug 16 05:49:33 PM PDT 24 |
Aug 16 05:49:34 PM PDT 24 |
32826256 ps |
| T146 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4263352662 |
|
|
Aug 16 05:49:05 PM PDT 24 |
Aug 16 05:49:07 PM PDT 24 |
316055910 ps |
| T954 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2467469528 |
|
|
Aug 16 05:49:18 PM PDT 24 |
Aug 16 05:49:22 PM PDT 24 |
1531566383 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1398725787 |
|
|
Aug 16 05:51:07 PM PDT 24 |
Aug 16 05:51:08 PM PDT 24 |
22000722 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3265369259 |
|
|
Aug 16 05:49:09 PM PDT 24 |
Aug 16 05:49:12 PM PDT 24 |
353803774 ps |
| T957 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.307529189 |
|
|
Aug 16 05:51:27 PM PDT 24 |
Aug 16 05:51:31 PM PDT 24 |
138212091 ps |
| T151 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.925107304 |
|
|
Aug 16 05:50:38 PM PDT 24 |
Aug 16 05:50:40 PM PDT 24 |
769227077 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3791917137 |
|
|
Aug 16 05:49:36 PM PDT 24 |
Aug 16 05:49:37 PM PDT 24 |
19410366 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2305934619 |
|
|
Aug 16 05:49:15 PM PDT 24 |
Aug 16 05:49:17 PM PDT 24 |
204430279 ps |
| T98 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1142182403 |
|
|
Aug 16 05:50:10 PM PDT 24 |
Aug 16 05:50:11 PM PDT 24 |
21964497 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2804243799 |
|
|
Aug 16 05:50:23 PM PDT 24 |
Aug 16 05:50:24 PM PDT 24 |
31469842 ps |
| T961 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2989523615 |
|
|
Aug 16 05:49:35 PM PDT 24 |
Aug 16 05:49:40 PM PDT 24 |
1442572924 ps |
| T152 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.845814571 |
|
|
Aug 16 05:50:32 PM PDT 24 |
Aug 16 05:50:34 PM PDT 24 |
174520991 ps |
| T148 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.564315291 |
|
|
Aug 16 05:49:17 PM PDT 24 |
Aug 16 05:49:19 PM PDT 24 |
266027550 ps |
| T962 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2786025696 |
|
|
Aug 16 05:49:39 PM PDT 24 |
Aug 16 05:49:40 PM PDT 24 |
48853426 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3827336943 |
|
|
Aug 16 05:49:13 PM PDT 24 |
Aug 16 05:49:17 PM PDT 24 |
1224751312 ps |
| T99 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1162342825 |
|
|
Aug 16 05:49:33 PM PDT 24 |
Aug 16 05:50:27 PM PDT 24 |
7355210132 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2846603491 |
|
|
Aug 16 05:49:47 PM PDT 24 |
Aug 16 05:49:48 PM PDT 24 |
16952659 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1721487439 |
|
|
Aug 16 05:50:37 PM PDT 24 |
Aug 16 05:51:05 PM PDT 24 |
14170020876 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2844317323 |
|
|
Aug 16 05:51:41 PM PDT 24 |
Aug 16 05:51:41 PM PDT 24 |
130968522 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3660247857 |
|
|
Aug 16 05:50:37 PM PDT 24 |
Aug 16 05:51:29 PM PDT 24 |
7195979007 ps |
| T156 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2505363858 |
|
|
Aug 16 05:51:45 PM PDT 24 |
Aug 16 05:51:47 PM PDT 24 |
339803471 ps |
| T965 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4055169563 |
|
|
Aug 16 05:49:11 PM PDT 24 |
Aug 16 05:49:12 PM PDT 24 |
23656558 ps |
| T102 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1471586715 |
|
|
Aug 16 05:50:10 PM PDT 24 |
Aug 16 05:50:11 PM PDT 24 |
14950150 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1564906940 |
|
|
Aug 16 05:49:09 PM PDT 24 |
Aug 16 05:49:13 PM PDT 24 |
120896826 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3288330975 |
|
|
Aug 16 05:50:19 PM PDT 24 |
Aug 16 05:50:21 PM PDT 24 |
149134749 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3617417453 |
|
|
Aug 16 05:50:08 PM PDT 24 |
Aug 16 05:50:12 PM PDT 24 |
75815374 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1427046755 |
|
|
Aug 16 05:51:07 PM PDT 24 |
Aug 16 05:51:35 PM PDT 24 |
3809272178 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4246025515 |
|
|
Aug 16 05:50:10 PM PDT 24 |
Aug 16 05:50:11 PM PDT 24 |
27203973 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.650255285 |
|
|
Aug 16 05:49:17 PM PDT 24 |
Aug 16 05:49:20 PM PDT 24 |
184525910 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3837524349 |
|
|
Aug 16 05:49:35 PM PDT 24 |
Aug 16 05:49:40 PM PDT 24 |
1459348965 ps |
| T972 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3943093627 |
|
|
Aug 16 05:49:16 PM PDT 24 |
Aug 16 05:49:20 PM PDT 24 |
676515963 ps |
| T973 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.493859476 |
|
|
Aug 16 05:49:16 PM PDT 24 |
Aug 16 05:49:19 PM PDT 24 |
692033210 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1933243975 |
|
|
Aug 16 05:49:20 PM PDT 24 |
Aug 16 05:49:23 PM PDT 24 |
473627160 ps |
| T975 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2969375327 |
|
|
Aug 16 05:50:34 PM PDT 24 |
Aug 16 05:50:38 PM PDT 24 |
1404470408 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2501840113 |
|
|
Aug 16 05:51:38 PM PDT 24 |
Aug 16 05:52:07 PM PDT 24 |
14798737657 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1218171060 |
|
|
Aug 16 05:49:11 PM PDT 24 |
Aug 16 05:49:12 PM PDT 24 |
15984472 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4105108666 |
|
|
Aug 16 05:51:40 PM PDT 24 |
Aug 16 05:51:41 PM PDT 24 |
34012854 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1010964990 |
|
|
Aug 16 05:50:19 PM PDT 24 |
Aug 16 05:50:21 PM PDT 24 |
264687334 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3466323417 |
|
|
Aug 16 05:49:11 PM PDT 24 |
Aug 16 05:49:12 PM PDT 24 |
54608126 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1919424971 |
|
|
Aug 16 05:50:10 PM PDT 24 |
Aug 16 05:50:12 PM PDT 24 |
45138340 ps |
| T117 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.396593872 |
|
|
Aug 16 05:50:23 PM PDT 24 |
Aug 16 05:50:24 PM PDT 24 |
43499313 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3072105619 |
|
|
Aug 16 05:51:35 PM PDT 24 |
Aug 16 05:51:36 PM PDT 24 |
28890234 ps |
| T981 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1730705384 |
|
|
Aug 16 05:49:09 PM PDT 24 |
Aug 16 05:49:13 PM PDT 24 |
271597332 ps |
| T982 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2171591183 |
|
|
Aug 16 05:50:21 PM PDT 24 |
Aug 16 05:50:22 PM PDT 24 |
40953301 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2629168752 |
|
|
Aug 16 05:52:02 PM PDT 24 |
Aug 16 05:52:04 PM PDT 24 |
596350704 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1903475424 |
|
|
Aug 16 05:50:10 PM PDT 24 |
Aug 16 05:50:14 PM PDT 24 |
293759653 ps |
| T155 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1056628498 |
|
|
Aug 16 05:49:14 PM PDT 24 |
Aug 16 05:49:16 PM PDT 24 |
628083486 ps |
| T985 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.778571409 |
|
|
Aug 16 05:49:08 PM PDT 24 |
Aug 16 05:49:13 PM PDT 24 |
693785208 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4171875271 |
|
|
Aug 16 05:49:16 PM PDT 24 |
Aug 16 05:49:17 PM PDT 24 |
111196779 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.764211927 |
|
|
Aug 16 05:51:33 PM PDT 24 |
Aug 16 05:52:22 PM PDT 24 |
7269489000 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3987329710 |
|
|
Aug 16 05:51:31 PM PDT 24 |
Aug 16 05:51:32 PM PDT 24 |
12451358 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3615349524 |
|
|
Aug 16 05:50:37 PM PDT 24 |
Aug 16 05:50:39 PM PDT 24 |
750579805 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1164686195 |
|
|
Aug 16 05:50:23 PM PDT 24 |
Aug 16 05:51:18 PM PDT 24 |
28211606866 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1714792688 |
|
|
Aug 16 05:51:06 PM PDT 24 |
Aug 16 05:51:09 PM PDT 24 |
414221135 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4129433548 |
|
|
Aug 16 05:49:47 PM PDT 24 |
Aug 16 05:49:52 PM PDT 24 |
869649701 ps |
| T991 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1627105464 |
|
|
Aug 16 05:49:13 PM PDT 24 |
Aug 16 05:49:18 PM PDT 24 |
1491596474 ps |
| T992 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2647380445 |
|
|
Aug 16 05:51:29 PM PDT 24 |
Aug 16 05:51:34 PM PDT 24 |
14821568 ps |
| T993 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2892472551 |
|
|
Aug 16 05:49:12 PM PDT 24 |
Aug 16 05:49:13 PM PDT 24 |
14299329 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4175315540 |
|
|
Aug 16 05:49:21 PM PDT 24 |
Aug 16 05:49:25 PM PDT 24 |
727726780 ps |
| T995 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1440205899 |
|
|
Aug 16 05:49:14 PM PDT 24 |
Aug 16 05:49:19 PM PDT 24 |
164299680 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3755384407 |
|
|
Aug 16 05:50:41 PM PDT 24 |
Aug 16 05:50:42 PM PDT 24 |
45920904 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.62985981 |
|
|
Aug 16 05:51:56 PM PDT 24 |
Aug 16 05:51:56 PM PDT 24 |
47081847 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2854899854 |
|
|
Aug 16 05:49:40 PM PDT 24 |
Aug 16 05:49:41 PM PDT 24 |
21672730 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.490301984 |
|
|
Aug 16 05:50:21 PM PDT 24 |
Aug 16 05:50:22 PM PDT 24 |
55945360 ps |
| T1000 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.838284836 |
|
|
Aug 16 05:49:43 PM PDT 24 |
Aug 16 05:49:43 PM PDT 24 |
15003830 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1609078250 |
|
|
Aug 16 05:49:09 PM PDT 24 |
Aug 16 05:49:10 PM PDT 24 |
15286406 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3578704907 |
|
|
Aug 16 05:50:34 PM PDT 24 |
Aug 16 05:50:35 PM PDT 24 |
46093776 ps |
| T1003 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3565168692 |
|
|
Aug 16 05:50:10 PM PDT 24 |
Aug 16 05:50:11 PM PDT 24 |
23643323 ps |
| T153 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.106370572 |
|
|
Aug 16 05:51:43 PM PDT 24 |
Aug 16 05:51:45 PM PDT 24 |
883974181 ps |
| T1004 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1183633781 |
|
|
Aug 16 05:50:07 PM PDT 24 |
Aug 16 05:50:07 PM PDT 24 |
15620929 ps |
| T114 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2828614896 |
|
|
Aug 16 05:49:15 PM PDT 24 |
Aug 16 05:49:43 PM PDT 24 |
12743324205 ps |
| T115 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1831432086 |
|
|
Aug 16 05:51:13 PM PDT 24 |
Aug 16 05:51:42 PM PDT 24 |
3709422528 ps |
| T1005 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1618881237 |
|
|
Aug 16 05:51:30 PM PDT 24 |
Aug 16 05:51:33 PM PDT 24 |
104365161 ps |