Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	366046896	1			T1	321504		T4	267646		T5	20046
instr_valid_dis	313455569	1			T1	7442		T4	9772		T5	20046
instr_en	41575618	1			T1	82		T4	257874		T19	225240

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	21932568	1			T1	120282		T4	38154		T19	30054
sram_ifetch_valid_disable	306352981	1			T1	36230		T4	151194		T5	20046
sram_ifetch_enable	37761347	1			T1	164992		T4	78298		T19	56078

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	366046896	1			T1	321504		T4	267646		T5	20046
hw_debug_en_valid_off	315971952	1			T1	149278		T4	45282		T5	20046
hw_debug_en_on	31587672	1			T1	36546		T4	147442		T19	63590

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	306352981	1			T1	36230		T4	151194		T5	20046
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	290201739	1			T1	7442		T4	9772		T5	20046
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11878931	1			T4	141422		T19	139108		T10	343634
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	11611152	1			T1	2114		T4	23450		T19	30054
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2691094	1			T20	49284		T158	11472		T160	39182
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	8083452	1			T4	23450		T19	30054		T10	13006
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7675050	1			T1	16546		T4	14704		T41	40568
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	5060134	1			T41	40568		T68	5958		T163	18892
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1761304	1			T4	14704		T20	35462		T158	1770
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10440698	1			T4	97834		T19	63590		T10	261546
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4460016	1			T41	16960		T20	80904		T159	27054
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4590844	1			T4	97834		T19	63590		T10	261546

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	18868767	1			T1	82		T4	78298		T19	56078
lc_exec_en	13471924	1			T1	20000		T4	34904		T10	19412
valid_exec_dis	305048443	1			T1	36230		T4	21754		T5	20046
invalid_exec_dis	59693915	1			T1	285274		T4	116452		T19	86132