Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	150698842	1			T1	59973		T4	66035		T5	9139
triple_byte_access	2851025	1			T1	1265		T4	1363		T5	183
halfword_access	4380919	1			T1	1819		T4	2124		T5	267
byte_access	6153932	1			T1	2380		T4	2607		T5	349
zero_access	1885997	1			T1	566		T4	684		T5	85

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82894005

1

T1

34105

T4

46009

T5

4991

auto[1]

83076710

1

T1

31898

T4

26804

T5

5032

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75099308	1			T1	30991		T4	41757		T5	4546
auto[0]	triple_byte_access	1355643	1			T1	659		T4	864		T5	88
auto[0]	halfword_access	2138354	1			T1	931		T4	1334		T5	132
auto[0]	byte_access	3160745	1			T1	1247		T4	1625		T5	177
auto[0]	zero_access	1139955	1			T1	277		T4	429		T5	48
auto[1]	word_access	75599534	1			T1	28982		T4	24278		T5	4593
auto[1]	triple_byte_access	1495382	1			T1	606		T4	499		T5	95
auto[1]	halfword_access	2242565	1			T1	888		T4	790		T5	135
auto[1]	byte_access	2993187	1			T1	1133		T4	982		T5	172
auto[1]	zero_access	746042	1			T1	289		T4	255		T5	37