| T800 |
/workspace/coverage/default/37.sram_ctrl_alert_test.2547180624 |
|
|
Aug 17 04:59:11 PM PDT 24 |
Aug 17 04:59:12 PM PDT 24 |
44155180 ps |
| T801 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2280077115 |
|
|
Aug 17 04:56:07 PM PDT 24 |
Aug 17 05:27:48 PM PDT 24 |
41349728489 ps |
| T802 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3538672951 |
|
|
Aug 17 04:56:19 PM PDT 24 |
Aug 17 04:57:12 PM PDT 24 |
508997999 ps |
| T803 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4044722288 |
|
|
Aug 17 04:56:25 PM PDT 24 |
Aug 17 05:06:41 PM PDT 24 |
17884639181 ps |
| T804 |
/workspace/coverage/default/3.sram_ctrl_stress_all.3728661144 |
|
|
Aug 17 04:56:17 PM PDT 24 |
Aug 17 05:42:34 PM PDT 24 |
27756353847 ps |
| T805 |
/workspace/coverage/default/47.sram_ctrl_smoke.2796376463 |
|
|
Aug 17 05:00:25 PM PDT 24 |
Aug 17 05:00:32 PM PDT 24 |
1386472772 ps |
| T806 |
/workspace/coverage/default/49.sram_ctrl_smoke.941221960 |
|
|
Aug 17 05:00:39 PM PDT 24 |
Aug 17 05:00:58 PM PDT 24 |
554171614 ps |
| T807 |
/workspace/coverage/default/16.sram_ctrl_bijection.1209506855 |
|
|
Aug 17 04:57:14 PM PDT 24 |
Aug 17 05:20:53 PM PDT 24 |
84969442207 ps |
| T808 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1813721540 |
|
|
Aug 17 04:59:09 PM PDT 24 |
Aug 17 05:01:09 PM PDT 24 |
2531219964 ps |
| T809 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3575268664 |
|
|
Aug 17 04:57:47 PM PDT 24 |
Aug 17 04:59:53 PM PDT 24 |
780827109 ps |
| T810 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2370879911 |
|
|
Aug 17 04:57:38 PM PDT 24 |
Aug 17 05:00:47 PM PDT 24 |
5556896111 ps |
| T811 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2677959589 |
|
|
Aug 17 04:57:44 PM PDT 24 |
Aug 17 04:58:35 PM PDT 24 |
6123267139 ps |
| T812 |
/workspace/coverage/default/3.sram_ctrl_alert_test.243560610 |
|
|
Aug 17 04:56:16 PM PDT 24 |
Aug 17 04:56:17 PM PDT 24 |
23336774 ps |
| T813 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.820032571 |
|
|
Aug 17 04:59:40 PM PDT 24 |
Aug 17 05:01:04 PM PDT 24 |
5485369718 ps |
| T814 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4275475359 |
|
|
Aug 17 04:57:29 PM PDT 24 |
Aug 17 04:59:01 PM PDT 24 |
1512526126 ps |
| T815 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1768174691 |
|
|
Aug 17 04:57:28 PM PDT 24 |
Aug 17 05:01:42 PM PDT 24 |
10204687754 ps |
| T816 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3633250965 |
|
|
Aug 17 04:58:40 PM PDT 24 |
Aug 17 04:58:46 PM PDT 24 |
681014246 ps |
| T817 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3233780895 |
|
|
Aug 17 04:59:27 PM PDT 24 |
Aug 17 04:59:30 PM PDT 24 |
1409759127 ps |
| T818 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1807964469 |
|
|
Aug 17 04:57:36 PM PDT 24 |
Aug 17 04:57:42 PM PDT 24 |
699796183 ps |
| T819 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2423008072 |
|
|
Aug 17 04:56:59 PM PDT 24 |
Aug 17 04:57:30 PM PDT 24 |
872015671 ps |
| T820 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3441914212 |
|
|
Aug 17 04:57:20 PM PDT 24 |
Aug 17 05:02:19 PM PDT 24 |
5087943647 ps |
| T821 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1889587590 |
|
|
Aug 17 04:59:41 PM PDT 24 |
Aug 17 05:04:07 PM PDT 24 |
4869917257 ps |
| T822 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3384820967 |
|
|
Aug 17 04:57:27 PM PDT 24 |
Aug 17 05:00:11 PM PDT 24 |
30056614441 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_smoke.4117800465 |
|
|
Aug 17 04:56:42 PM PDT 24 |
Aug 17 04:57:28 PM PDT 24 |
425937266 ps |
| T824 |
/workspace/coverage/default/13.sram_ctrl_executable.905579343 |
|
|
Aug 17 04:57:13 PM PDT 24 |
Aug 17 04:57:35 PM PDT 24 |
5747474474 ps |
| T825 |
/workspace/coverage/default/15.sram_ctrl_bijection.2459444975 |
|
|
Aug 17 04:57:15 PM PDT 24 |
Aug 17 05:26:10 PM PDT 24 |
24992492180 ps |
| T826 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.917753174 |
|
|
Aug 17 04:56:14 PM PDT 24 |
Aug 17 04:57:00 PM PDT 24 |
8866048979 ps |
| T827 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1822334737 |
|
|
Aug 17 04:58:42 PM PDT 24 |
Aug 17 06:19:40 PM PDT 24 |
239239702890 ps |
| T828 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.507372565 |
|
|
Aug 17 04:58:09 PM PDT 24 |
Aug 17 04:58:48 PM PDT 24 |
21674918159 ps |
| T829 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.265484242 |
|
|
Aug 17 05:00:16 PM PDT 24 |
Aug 17 05:26:45 PM PDT 24 |
31615224414 ps |
| T830 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.922429503 |
|
|
Aug 17 04:56:01 PM PDT 24 |
Aug 17 04:57:27 PM PDT 24 |
3079447927 ps |
| T831 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.4263240190 |
|
|
Aug 17 04:56:09 PM PDT 24 |
Aug 17 05:13:54 PM PDT 24 |
11963625242 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1510751020 |
|
|
Aug 17 04:57:51 PM PDT 24 |
Aug 17 05:00:22 PM PDT 24 |
48594588100 ps |
| T833 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2608197251 |
|
|
Aug 17 04:57:54 PM PDT 24 |
Aug 17 05:00:35 PM PDT 24 |
22748426232 ps |
| T834 |
/workspace/coverage/default/20.sram_ctrl_executable.2330398364 |
|
|
Aug 17 04:57:33 PM PDT 24 |
Aug 17 05:01:59 PM PDT 24 |
8578749399 ps |
| T27 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2280168222 |
|
|
Aug 17 04:56:17 PM PDT 24 |
Aug 17 04:56:19 PM PDT 24 |
459484611 ps |
| T835 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.754426147 |
|
|
Aug 17 04:57:08 PM PDT 24 |
Aug 17 05:03:49 PM PDT 24 |
17787703122 ps |
| T836 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.147181644 |
|
|
Aug 17 04:59:40 PM PDT 24 |
Aug 17 05:05:35 PM PDT 24 |
86134526128 ps |
| T837 |
/workspace/coverage/default/19.sram_ctrl_regwen.3101549089 |
|
|
Aug 17 04:57:30 PM PDT 24 |
Aug 17 05:15:49 PM PDT 24 |
14659456702 ps |
| T838 |
/workspace/coverage/default/18.sram_ctrl_alert_test.165739556 |
|
|
Aug 17 04:57:29 PM PDT 24 |
Aug 17 04:57:30 PM PDT 24 |
26983474 ps |
| T839 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.421615362 |
|
|
Aug 17 04:57:51 PM PDT 24 |
Aug 17 05:05:18 PM PDT 24 |
21623863443 ps |
| T840 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1414173895 |
|
|
Aug 17 04:57:39 PM PDT 24 |
Aug 17 04:58:00 PM PDT 24 |
1962752472 ps |
| T841 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3021102056 |
|
|
Aug 17 04:58:09 PM PDT 24 |
Aug 17 04:58:41 PM PDT 24 |
1997064521 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_regwen.4146465072 |
|
|
Aug 17 04:57:36 PM PDT 24 |
Aug 17 05:18:14 PM PDT 24 |
3775962591 ps |
| T843 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1386060093 |
|
|
Aug 17 04:57:21 PM PDT 24 |
Aug 17 04:59:58 PM PDT 24 |
1567585609 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1919357193 |
|
|
Aug 17 04:58:51 PM PDT 24 |
Aug 17 05:00:00 PM PDT 24 |
12574064829 ps |
| T845 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1119533936 |
|
|
Aug 17 04:58:56 PM PDT 24 |
Aug 17 04:59:55 PM PDT 24 |
3127307899 ps |
| T846 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3120405821 |
|
|
Aug 17 04:57:08 PM PDT 24 |
Aug 17 04:57:08 PM PDT 24 |
37607894 ps |
| T847 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3228069710 |
|
|
Aug 17 04:56:01 PM PDT 24 |
Aug 17 04:56:05 PM PDT 24 |
1412701045 ps |
| T848 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1298069342 |
|
|
Aug 17 04:58:24 PM PDT 24 |
Aug 17 05:04:55 PM PDT 24 |
6987709067 ps |
| T849 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3130331183 |
|
|
Aug 17 04:59:13 PM PDT 24 |
Aug 17 04:59:34 PM PDT 24 |
1356458184 ps |
| T850 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.866258117 |
|
|
Aug 17 04:59:40 PM PDT 24 |
Aug 17 05:28:14 PM PDT 24 |
60019871009 ps |
| T851 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2505478129 |
|
|
Aug 17 04:56:26 PM PDT 24 |
Aug 17 04:56:45 PM PDT 24 |
3793057184 ps |
| T852 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1213446679 |
|
|
Aug 17 04:57:16 PM PDT 24 |
Aug 17 05:03:44 PM PDT 24 |
7150727792 ps |
| T853 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1017085493 |
|
|
Aug 17 04:58:39 PM PDT 24 |
Aug 17 05:04:24 PM PDT 24 |
20684118864 ps |
| T854 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1356718077 |
|
|
Aug 17 04:59:11 PM PDT 24 |
Aug 17 05:01:24 PM PDT 24 |
6608799321 ps |
| T855 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2769952813 |
|
|
Aug 17 05:00:49 PM PDT 24 |
Aug 17 05:00:53 PM PDT 24 |
346510154 ps |
| T856 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1484015557 |
|
|
Aug 17 04:57:28 PM PDT 24 |
Aug 17 05:04:59 PM PDT 24 |
68594419822 ps |
| T857 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.444981888 |
|
|
Aug 17 04:58:57 PM PDT 24 |
Aug 17 04:59:26 PM PDT 24 |
2884087238 ps |
| T858 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1451454035 |
|
|
Aug 17 04:57:43 PM PDT 24 |
Aug 17 04:58:54 PM PDT 24 |
2988396629 ps |
| T859 |
/workspace/coverage/default/14.sram_ctrl_bijection.2584027328 |
|
|
Aug 17 04:57:16 PM PDT 24 |
Aug 17 05:25:30 PM PDT 24 |
81306094733 ps |
| T860 |
/workspace/coverage/default/8.sram_ctrl_smoke.3663126718 |
|
|
Aug 17 04:56:48 PM PDT 24 |
Aug 17 04:57:49 PM PDT 24 |
1339133929 ps |
| T861 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3005848143 |
|
|
Aug 17 04:58:32 PM PDT 24 |
Aug 17 04:58:42 PM PDT 24 |
1393258954 ps |
| T862 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1366061532 |
|
|
Aug 17 05:00:38 PM PDT 24 |
Aug 17 05:00:55 PM PDT 24 |
4355817929 ps |
| T863 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3502016596 |
|
|
Aug 17 05:00:32 PM PDT 24 |
Aug 17 05:01:04 PM PDT 24 |
993434666 ps |
| T864 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.363881283 |
|
|
Aug 17 04:57:27 PM PDT 24 |
Aug 17 04:58:15 PM PDT 24 |
3449175893 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2405648357 |
|
|
Aug 17 05:00:27 PM PDT 24 |
Aug 17 05:01:46 PM PDT 24 |
12564577837 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1684036556 |
|
|
Aug 17 04:57:16 PM PDT 24 |
Aug 17 04:57:51 PM PDT 24 |
2978163586 ps |
| T867 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2645830776 |
|
|
Aug 17 04:59:50 PM PDT 24 |
Aug 17 05:01:29 PM PDT 24 |
47136125711 ps |
| T868 |
/workspace/coverage/default/13.sram_ctrl_regwen.3100325311 |
|
|
Aug 17 04:57:15 PM PDT 24 |
Aug 17 05:10:56 PM PDT 24 |
15055293446 ps |
| T869 |
/workspace/coverage/default/10.sram_ctrl_bijection.3903614751 |
|
|
Aug 17 04:57:07 PM PDT 24 |
Aug 17 05:17:28 PM PDT 24 |
17721730009 ps |
| T870 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1699211631 |
|
|
Aug 17 04:57:09 PM PDT 24 |
Aug 17 04:57:26 PM PDT 24 |
4084370740 ps |
| T871 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3716402051 |
|
|
Aug 17 04:56:05 PM PDT 24 |
Aug 17 04:58:48 PM PDT 24 |
28786213738 ps |
| T108 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2775535171 |
|
|
Aug 17 04:57:48 PM PDT 24 |
Aug 17 05:00:10 PM PDT 24 |
2531123356 ps |
| T872 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2437536709 |
|
|
Aug 17 04:56:16 PM PDT 24 |
Aug 17 05:23:38 PM PDT 24 |
22837171488 ps |
| T873 |
/workspace/coverage/default/36.sram_ctrl_smoke.576610819 |
|
|
Aug 17 04:58:57 PM PDT 24 |
Aug 17 04:59:08 PM PDT 24 |
618740551 ps |
| T874 |
/workspace/coverage/default/7.sram_ctrl_bijection.1884095727 |
|
|
Aug 17 04:56:40 PM PDT 24 |
Aug 17 05:29:56 PM PDT 24 |
442603020517 ps |
| T875 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1428001997 |
|
|
Aug 17 04:57:15 PM PDT 24 |
Aug 17 04:57:31 PM PDT 24 |
817719124 ps |
| T876 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3103743728 |
|
|
Aug 17 04:56:40 PM PDT 24 |
Aug 17 04:56:49 PM PDT 24 |
685501185 ps |
| T877 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3634543943 |
|
|
Aug 17 04:56:13 PM PDT 24 |
Aug 17 04:57:27 PM PDT 24 |
5343923217 ps |
| T878 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3623715013 |
|
|
Aug 17 04:59:26 PM PDT 24 |
Aug 17 05:07:00 PM PDT 24 |
37149065025 ps |
| T879 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1918951652 |
|
|
Aug 17 04:59:21 PM PDT 24 |
Aug 17 04:59:21 PM PDT 24 |
34695169 ps |
| T880 |
/workspace/coverage/default/21.sram_ctrl_executable.46567275 |
|
|
Aug 17 04:57:32 PM PDT 24 |
Aug 17 05:24:28 PM PDT 24 |
75914386412 ps |
| T881 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1793852159 |
|
|
Aug 17 04:57:14 PM PDT 24 |
Aug 17 06:16:55 PM PDT 24 |
40031508912 ps |
| T882 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2176638879 |
|
|
Aug 17 04:58:48 PM PDT 24 |
Aug 17 05:01:46 PM PDT 24 |
57581765587 ps |
| T883 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1433002030 |
|
|
Aug 17 05:00:35 PM PDT 24 |
Aug 17 05:01:22 PM PDT 24 |
8802884579 ps |
| T884 |
/workspace/coverage/default/32.sram_ctrl_smoke.1156444305 |
|
|
Aug 17 04:58:32 PM PDT 24 |
Aug 17 04:58:51 PM PDT 24 |
3251739165 ps |
| T885 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1872304331 |
|
|
Aug 17 04:56:10 PM PDT 24 |
Aug 17 05:03:04 PM PDT 24 |
5765137198 ps |
| T886 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3718035719 |
|
|
Aug 17 04:59:12 PM PDT 24 |
Aug 17 04:59:16 PM PDT 24 |
1068652880 ps |
| T887 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3129482830 |
|
|
Aug 17 04:59:03 PM PDT 24 |
Aug 17 05:00:53 PM PDT 24 |
802087633 ps |
| T888 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1642076648 |
|
|
Aug 17 04:57:00 PM PDT 24 |
Aug 17 05:01:28 PM PDT 24 |
27710331355 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3751422403 |
|
|
Aug 17 04:57:07 PM PDT 24 |
Aug 17 04:57:08 PM PDT 24 |
92246679 ps |
| T890 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1764996972 |
|
|
Aug 17 04:57:01 PM PDT 24 |
Aug 17 04:59:54 PM PDT 24 |
5016445558 ps |
| T891 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2305558585 |
|
|
Aug 17 04:56:16 PM PDT 24 |
Aug 17 06:34:13 PM PDT 24 |
324742147163 ps |
| T892 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.136364822 |
|
|
Aug 17 04:56:39 PM PDT 24 |
Aug 17 05:10:48 PM PDT 24 |
14362299853 ps |
| T893 |
/workspace/coverage/default/34.sram_ctrl_partial_access.636598907 |
|
|
Aug 17 04:58:48 PM PDT 24 |
Aug 17 04:59:10 PM PDT 24 |
1320963761 ps |
| T894 |
/workspace/coverage/default/24.sram_ctrl_regwen.3664786528 |
|
|
Aug 17 04:57:48 PM PDT 24 |
Aug 17 05:08:23 PM PDT 24 |
2547042304 ps |
| T895 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.3411873276 |
|
|
Aug 17 04:58:24 PM PDT 24 |
Aug 17 05:02:45 PM PDT 24 |
4066436635 ps |
| T896 |
/workspace/coverage/default/8.sram_ctrl_alert_test.21303995 |
|
|
Aug 17 04:57:00 PM PDT 24 |
Aug 17 04:57:01 PM PDT 24 |
60475496 ps |
| T897 |
/workspace/coverage/default/22.sram_ctrl_partial_access.2453738653 |
|
|
Aug 17 04:57:41 PM PDT 24 |
Aug 17 04:57:54 PM PDT 24 |
7709794237 ps |
| T898 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.97842339 |
|
|
Aug 17 04:57:47 PM PDT 24 |
Aug 17 05:03:00 PM PDT 24 |
123565025470 ps |
| T899 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3986498236 |
|
|
Aug 17 04:59:21 PM PDT 24 |
Aug 17 05:00:01 PM PDT 24 |
3423028600 ps |
| T900 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2655461708 |
|
|
Aug 17 04:59:56 PM PDT 24 |
Aug 17 04:59:57 PM PDT 24 |
51875165 ps |
| T901 |
/workspace/coverage/default/42.sram_ctrl_smoke.2441913742 |
|
|
Aug 17 04:59:40 PM PDT 24 |
Aug 17 04:59:45 PM PDT 24 |
439548261 ps |
| T902 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.671104470 |
|
|
Aug 17 04:56:16 PM PDT 24 |
Aug 17 05:03:29 PM PDT 24 |
39249038236 ps |
| T903 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.599630914 |
|
|
Aug 17 04:58:52 PM PDT 24 |
Aug 17 05:02:33 PM PDT 24 |
6426605254 ps |
| T904 |
/workspace/coverage/default/15.sram_ctrl_regwen.2477410020 |
|
|
Aug 17 04:57:15 PM PDT 24 |
Aug 17 05:02:15 PM PDT 24 |
11150754218 ps |
| T905 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2074266181 |
|
|
Aug 17 04:58:33 PM PDT 24 |
Aug 17 06:14:51 PM PDT 24 |
85123244335 ps |
| T906 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2391155736 |
|
|
Aug 17 04:58:40 PM PDT 24 |
Aug 17 04:59:39 PM PDT 24 |
20167325807 ps |
| T907 |
/workspace/coverage/default/42.sram_ctrl_stress_all.771108076 |
|
|
Aug 17 04:59:48 PM PDT 24 |
Aug 17 06:21:26 PM PDT 24 |
137893944173 ps |
| T908 |
/workspace/coverage/default/15.sram_ctrl_smoke.2067367463 |
|
|
Aug 17 04:57:12 PM PDT 24 |
Aug 17 04:57:26 PM PDT 24 |
1019540676 ps |
| T909 |
/workspace/coverage/default/17.sram_ctrl_regwen.1491551820 |
|
|
Aug 17 04:57:21 PM PDT 24 |
Aug 17 05:19:23 PM PDT 24 |
7457359192 ps |
| T910 |
/workspace/coverage/default/29.sram_ctrl_smoke.1500562520 |
|
|
Aug 17 04:58:12 PM PDT 24 |
Aug 17 04:58:19 PM PDT 24 |
1276333697 ps |
| T911 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2685808191 |
|
|
Aug 17 04:58:51 PM PDT 24 |
Aug 17 04:59:06 PM PDT 24 |
4635757652 ps |
| T912 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2875800707 |
|
|
Aug 17 04:59:04 PM PDT 24 |
Aug 17 05:01:33 PM PDT 24 |
19044547744 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_executable.462064112 |
|
|
Aug 17 04:58:08 PM PDT 24 |
Aug 17 05:13:15 PM PDT 24 |
53887841197 ps |
| T914 |
/workspace/coverage/default/39.sram_ctrl_smoke.2035303686 |
|
|
Aug 17 04:59:20 PM PDT 24 |
Aug 17 04:59:59 PM PDT 24 |
1457515165 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_stress_all.4135552768 |
|
|
Aug 17 04:56:57 PM PDT 24 |
Aug 17 06:45:56 PM PDT 24 |
834602085452 ps |
| T916 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2234372438 |
|
|
Aug 17 04:56:17 PM PDT 24 |
Aug 17 05:01:40 PM PDT 24 |
4908914308 ps |
| T917 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.695613544 |
|
|
Aug 17 04:57:37 PM PDT 24 |
Aug 17 04:57:50 PM PDT 24 |
2756854082 ps |
| T918 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.358680717 |
|
|
Aug 17 05:00:28 PM PDT 24 |
Aug 17 05:00:36 PM PDT 24 |
3069573151 ps |
| T919 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.1185781874 |
|
|
Aug 17 04:57:29 PM PDT 24 |
Aug 17 04:57:32 PM PDT 24 |
1344151304 ps |
| T920 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1439299743 |
|
|
Aug 17 04:58:55 PM PDT 24 |
Aug 17 06:33:59 PM PDT 24 |
109539929601 ps |
| T921 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1159833417 |
|
|
Aug 17 04:58:55 PM PDT 24 |
Aug 17 05:28:46 PM PDT 24 |
233817877607 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.3851299780 |
|
|
Aug 17 05:00:30 PM PDT 24 |
Aug 17 05:03:16 PM PDT 24 |
27689662974 ps |
| T923 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1539701687 |
|
|
Aug 17 04:56:09 PM PDT 24 |
Aug 17 04:56:23 PM PDT 24 |
981636722 ps |
| T924 |
/workspace/coverage/default/12.sram_ctrl_smoke.2655507172 |
|
|
Aug 17 04:57:05 PM PDT 24 |
Aug 17 04:57:24 PM PDT 24 |
11980863572 ps |
| T925 |
/workspace/coverage/default/40.sram_ctrl_smoke.2438652450 |
|
|
Aug 17 04:59:20 PM PDT 24 |
Aug 17 05:00:47 PM PDT 24 |
1786277360 ps |
| T926 |
/workspace/coverage/default/1.sram_ctrl_executable.449663524 |
|
|
Aug 17 04:56:13 PM PDT 24 |
Aug 17 04:56:32 PM PDT 24 |
1087879996 ps |
| T927 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.137665808 |
|
|
Aug 17 04:58:25 PM PDT 24 |
Aug 17 05:06:31 PM PDT 24 |
31196247267 ps |
| T928 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1767802272 |
|
|
Aug 17 05:00:02 PM PDT 24 |
Aug 17 05:03:07 PM PDT 24 |
39756399855 ps |
| T929 |
/workspace/coverage/default/1.sram_ctrl_regwen.2569269692 |
|
|
Aug 17 04:56:11 PM PDT 24 |
Aug 17 05:22:20 PM PDT 24 |
29849710620 ps |
| T930 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3701455914 |
|
|
Aug 17 04:59:26 PM PDT 24 |
Aug 17 05:01:49 PM PDT 24 |
3090007585 ps |
| T28 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.4199569800 |
|
|
Aug 17 04:56:07 PM PDT 24 |
Aug 17 04:56:09 PM PDT 24 |
448622747 ps |
| T931 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2062330596 |
|
|
Aug 17 04:57:21 PM PDT 24 |
Aug 17 05:18:53 PM PDT 24 |
17068053050 ps |
| T932 |
/workspace/coverage/default/3.sram_ctrl_regwen.2052085938 |
|
|
Aug 17 04:56:14 PM PDT 24 |
Aug 17 05:14:12 PM PDT 24 |
7164104435 ps |
| T933 |
/workspace/coverage/default/46.sram_ctrl_stress_all.408195169 |
|
|
Aug 17 05:00:27 PM PDT 24 |
Aug 17 07:01:48 PM PDT 24 |
212012599206 ps |
| T934 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.4086158875 |
|
|
Aug 17 04:56:10 PM PDT 24 |
Aug 17 04:57:27 PM PDT 24 |
2358939984 ps |
| T935 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1428936989 |
|
|
Aug 17 04:58:22 PM PDT 24 |
Aug 17 04:58:23 PM PDT 24 |
25210328 ps |
| T936 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3818660468 |
|
|
Aug 17 04:58:42 PM PDT 24 |
Aug 17 04:59:02 PM PDT 24 |
2768125847 ps |
| T937 |
/workspace/coverage/default/43.sram_ctrl_executable.3458559046 |
|
|
Aug 17 04:59:48 PM PDT 24 |
Aug 17 05:24:29 PM PDT 24 |
22625495080 ps |
| T938 |
/workspace/coverage/default/2.sram_ctrl_smoke.2064515794 |
|
|
Aug 17 04:56:09 PM PDT 24 |
Aug 17 04:56:16 PM PDT 24 |
863333403 ps |
| T939 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3964858058 |
|
|
Aug 17 04:59:40 PM PDT 24 |
Aug 17 05:02:02 PM PDT 24 |
4882959568 ps |
| T940 |
/workspace/coverage/default/0.sram_ctrl_executable.1265353945 |
|
|
Aug 17 04:56:09 PM PDT 24 |
Aug 17 05:13:08 PM PDT 24 |
60085596934 ps |
| T941 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1704315976 |
|
|
Aug 17 04:59:33 PM PDT 24 |
Aug 17 05:23:37 PM PDT 24 |
20589446445 ps |
| T942 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.311253279 |
|
|
Aug 17 04:58:09 PM PDT 24 |
Aug 17 05:00:47 PM PDT 24 |
2871970661 ps |
| T943 |
/workspace/coverage/default/1.sram_ctrl_bijection.1726060439 |
|
|
Aug 17 04:56:06 PM PDT 24 |
Aug 17 05:07:35 PM PDT 24 |
39640931010 ps |
| T944 |
/workspace/coverage/default/32.sram_ctrl_bijection.611262152 |
|
|
Aug 17 04:58:32 PM PDT 24 |
Aug 17 05:12:42 PM PDT 24 |
14282489706 ps |
| T945 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.702791047 |
|
|
Aug 17 04:57:23 PM PDT 24 |
Aug 17 05:02:01 PM PDT 24 |
5872515470 ps |
| T946 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2968067697 |
|
|
Aug 17 04:59:20 PM PDT 24 |
Aug 17 05:03:32 PM PDT 24 |
11910111018 ps |
| T947 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3999055720 |
|
|
Aug 17 04:57:53 PM PDT 24 |
Aug 17 04:58:31 PM PDT 24 |
1464208198 ps |
| T948 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.191393733 |
|
|
Aug 17 04:59:34 PM PDT 24 |
Aug 17 04:59:41 PM PDT 24 |
693673349 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.687133449 |
|
|
Aug 17 05:59:58 PM PDT 24 |
Aug 17 05:59:59 PM PDT 24 |
24184686 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1309210893 |
|
|
Aug 17 06:00:33 PM PDT 24 |
Aug 17 06:01:00 PM PDT 24 |
18429282282 ps |
| T71 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.428045403 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:08 PM PDT 24 |
126073869 ps |
| T117 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3919806069 |
|
|
Aug 17 06:00:08 PM PDT 24 |
Aug 17 06:00:09 PM PDT 24 |
29939085 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2483796995 |
|
|
Aug 17 05:59:59 PM PDT 24 |
Aug 17 06:00:01 PM PDT 24 |
270193048 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3191608485 |
|
|
Aug 17 06:00:07 PM PDT 24 |
Aug 17 06:00:09 PM PDT 24 |
140195907 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3008392351 |
|
|
Aug 17 05:59:44 PM PDT 24 |
Aug 17 05:59:45 PM PDT 24 |
18240806 ps |
| T84 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4193721114 |
|
|
Aug 17 06:00:21 PM PDT 24 |
Aug 17 06:00:48 PM PDT 24 |
4039795769 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2907958512 |
|
|
Aug 17 05:59:39 PM PDT 24 |
Aug 17 05:59:40 PM PDT 24 |
46871838 ps |
| T119 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1812030654 |
|
|
Aug 17 06:00:33 PM PDT 24 |
Aug 17 06:00:34 PM PDT 24 |
72740205 ps |
| T128 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4292974408 |
|
|
Aug 17 05:59:40 PM PDT 24 |
Aug 17 05:59:41 PM PDT 24 |
29193976 ps |
| T120 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1445609096 |
|
|
Aug 17 05:59:47 PM PDT 24 |
Aug 17 05:59:48 PM PDT 24 |
12914767 ps |
| T949 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.561688487 |
|
|
Aug 17 06:00:15 PM PDT 24 |
Aug 17 06:00:19 PM PDT 24 |
3140411146 ps |
| T85 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1792201012 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:31 PM PDT 24 |
3876539172 ps |
| T86 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1484100352 |
|
|
Aug 17 05:59:49 PM PDT 24 |
Aug 17 05:59:50 PM PDT 24 |
34408876 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.78209104 |
|
|
Aug 17 05:59:39 PM PDT 24 |
Aug 17 05:59:43 PM PDT 24 |
44324374 ps |
| T121 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2271731855 |
|
|
Aug 17 06:00:13 PM PDT 24 |
Aug 17 06:00:14 PM PDT 24 |
19853685 ps |
| T951 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3384217701 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:08 PM PDT 24 |
33276179 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4087504243 |
|
|
Aug 17 06:00:09 PM PDT 24 |
Aug 17 06:00:14 PM PDT 24 |
733699653 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2526729022 |
|
|
Aug 17 06:00:07 PM PDT 24 |
Aug 17 06:00:11 PM PDT 24 |
351295639 ps |
| T152 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1724034807 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:24 PM PDT 24 |
352730951 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.416323370 |
|
|
Aug 17 05:59:46 PM PDT 24 |
Aug 17 05:59:48 PM PDT 24 |
510992137 ps |
| T87 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1873896693 |
|
|
Aug 17 06:00:22 PM PDT 24 |
Aug 17 06:00:23 PM PDT 24 |
14224637 ps |
| T146 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.988318789 |
|
|
Aug 17 06:00:10 PM PDT 24 |
Aug 17 06:00:13 PM PDT 24 |
483466344 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2273511987 |
|
|
Aug 17 06:00:33 PM PDT 24 |
Aug 17 06:00:34 PM PDT 24 |
59736399 ps |
| T956 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.776936155 |
|
|
Aug 17 06:00:07 PM PDT 24 |
Aug 17 06:00:10 PM PDT 24 |
703316180 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1997153230 |
|
|
Aug 17 05:59:40 PM PDT 24 |
Aug 17 06:00:12 PM PDT 24 |
15374785284 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.347135686 |
|
|
Aug 17 05:59:58 PM PDT 24 |
Aug 17 05:59:59 PM PDT 24 |
242330241 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2501921768 |
|
|
Aug 17 05:59:45 PM PDT 24 |
Aug 17 05:59:45 PM PDT 24 |
27561825 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2816138132 |
|
|
Aug 17 05:59:58 PM PDT 24 |
Aug 17 05:59:59 PM PDT 24 |
39403858 ps |
| T151 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3055712652 |
|
|
Aug 17 06:00:00 PM PDT 24 |
Aug 17 06:00:02 PM PDT 24 |
692937999 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3133643527 |
|
|
Aug 17 05:59:48 PM PDT 24 |
Aug 17 05:59:49 PM PDT 24 |
70288278 ps |
| T147 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1154503414 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:25 PM PDT 24 |
303055564 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1889440790 |
|
|
Aug 17 06:00:01 PM PDT 24 |
Aug 17 06:00:09 PM PDT 24 |
142607953 ps |
| T150 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1546577124 |
|
|
Aug 17 05:59:31 PM PDT 24 |
Aug 17 05:59:32 PM PDT 24 |
397710847 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2539184183 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:27 PM PDT 24 |
815187510 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1276530939 |
|
|
Aug 17 06:00:30 PM PDT 24 |
Aug 17 06:00:31 PM PDT 24 |
20087848 ps |
| T91 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3078293183 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:07 PM PDT 24 |
29705174 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.494525927 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:24 PM PDT 24 |
22177166 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3941463935 |
|
|
Aug 17 06:00:14 PM PDT 24 |
Aug 17 06:00:15 PM PDT 24 |
39356787 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3593867115 |
|
|
Aug 17 06:00:05 PM PDT 24 |
Aug 17 06:00:06 PM PDT 24 |
13619834 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1917223220 |
|
|
Aug 17 05:59:38 PM PDT 24 |
Aug 17 05:59:42 PM PDT 24 |
1379608485 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3029523224 |
|
|
Aug 17 05:59:46 PM PDT 24 |
Aug 17 06:00:38 PM PDT 24 |
14412536188 ps |
| T153 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3288401740 |
|
|
Aug 17 05:59:40 PM PDT 24 |
Aug 17 05:59:42 PM PDT 24 |
98342826 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3008135213 |
|
|
Aug 17 06:00:30 PM PDT 24 |
Aug 17 06:00:31 PM PDT 24 |
208579213 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.417739340 |
|
|
Aug 17 06:00:07 PM PDT 24 |
Aug 17 06:00:08 PM PDT 24 |
15079900 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.405020635 |
|
|
Aug 17 05:59:59 PM PDT 24 |
Aug 17 06:00:00 PM PDT 24 |
23882000 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.911144032 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:10 PM PDT 24 |
38732595 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2974825313 |
|
|
Aug 17 05:59:41 PM PDT 24 |
Aug 17 05:59:45 PM PDT 24 |
1667793117 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.970845193 |
|
|
Aug 17 06:00:29 PM PDT 24 |
Aug 17 06:00:32 PM PDT 24 |
30375353 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3289056866 |
|
|
Aug 17 05:59:46 PM PDT 24 |
Aug 17 05:59:49 PM PDT 24 |
531899746 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2818198697 |
|
|
Aug 17 05:59:39 PM PDT 24 |
Aug 17 05:59:40 PM PDT 24 |
24186756 ps |
| T95 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1930076251 |
|
|
Aug 17 06:00:32 PM PDT 24 |
Aug 17 06:01:03 PM PDT 24 |
14734818889 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3388595222 |
|
|
Aug 17 06:00:33 PM PDT 24 |
Aug 17 06:00:37 PM PDT 24 |
720411505 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3742850341 |
|
|
Aug 17 05:59:40 PM PDT 24 |
Aug 17 05:59:41 PM PDT 24 |
31896186 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4232042880 |
|
|
Aug 17 06:00:13 PM PDT 24 |
Aug 17 06:00:15 PM PDT 24 |
71512458 ps |
| T149 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.966179667 |
|
|
Aug 17 06:00:17 PM PDT 24 |
Aug 17 06:00:20 PM PDT 24 |
627971573 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1226561440 |
|
|
Aug 17 05:59:33 PM PDT 24 |
Aug 17 06:00:04 PM PDT 24 |
46077340041 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4139868146 |
|
|
Aug 17 05:59:39 PM PDT 24 |
Aug 17 05:59:42 PM PDT 24 |
126176889 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3737247711 |
|
|
Aug 17 05:59:47 PM PDT 24 |
Aug 17 05:59:48 PM PDT 24 |
17753858 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3052073266 |
|
|
Aug 17 06:00:27 PM PDT 24 |
Aug 17 06:00:28 PM PDT 24 |
52257676 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.132686747 |
|
|
Aug 17 05:59:46 PM PDT 24 |
Aug 17 05:59:48 PM PDT 24 |
207679607 ps |
| T154 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1536568981 |
|
|
Aug 17 06:00:30 PM PDT 24 |
Aug 17 06:00:33 PM PDT 24 |
971772267 ps |
| T980 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4136517600 |
|
|
Aug 17 06:00:30 PM PDT 24 |
Aug 17 06:00:30 PM PDT 24 |
16879216 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.860086394 |
|
|
Aug 17 05:59:39 PM PDT 24 |
Aug 17 05:59:45 PM PDT 24 |
837117387 ps |
| T982 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.820037395 |
|
|
Aug 17 06:00:05 PM PDT 24 |
Aug 17 06:00:05 PM PDT 24 |
47024925 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2142622003 |
|
|
Aug 17 05:59:40 PM PDT 24 |
Aug 17 05:59:42 PM PDT 24 |
133331950 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.126275650 |
|
|
Aug 17 05:59:44 PM PDT 24 |
Aug 17 05:59:48 PM PDT 24 |
427489720 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2273588561 |
|
|
Aug 17 06:00:14 PM PDT 24 |
Aug 17 06:00:17 PM PDT 24 |
358686544 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2818640333 |
|
|
Aug 17 06:00:29 PM PDT 24 |
Aug 17 06:00:30 PM PDT 24 |
17558228 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3846063053 |
|
|
Aug 17 06:00:29 PM PDT 24 |
Aug 17 06:00:33 PM PDT 24 |
251145756 ps |
| T988 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4267735661 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:27 PM PDT 24 |
653472742 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1342124008 |
|
|
Aug 17 06:00:22 PM PDT 24 |
Aug 17 06:00:27 PM PDT 24 |
774869095 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1914156243 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:24 PM PDT 24 |
67843193 ps |
| T96 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1609723947 |
|
|
Aug 17 06:00:12 PM PDT 24 |
Aug 17 06:00:12 PM PDT 24 |
140954612 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2067379769 |
|
|
Aug 17 05:59:59 PM PDT 24 |
Aug 17 06:00:04 PM PDT 24 |
144114834 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3957882428 |
|
|
Aug 17 06:00:30 PM PDT 24 |
Aug 17 06:00:34 PM PDT 24 |
364891309 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2744134274 |
|
|
Aug 17 06:00:14 PM PDT 24 |
Aug 17 06:00:15 PM PDT 24 |
17741552 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2042901043 |
|
|
Aug 17 06:00:31 PM PDT 24 |
Aug 17 06:00:31 PM PDT 24 |
27072716 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2994759929 |
|
|
Aug 17 06:00:26 PM PDT 24 |
Aug 17 06:00:27 PM PDT 24 |
21861059 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1945976469 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:26 PM PDT 24 |
715367882 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2060554258 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:08 PM PDT 24 |
890828659 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2001721896 |
|
|
Aug 17 06:00:22 PM PDT 24 |
Aug 17 06:00:28 PM PDT 24 |
250215580 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1170400651 |
|
|
Aug 17 06:00:02 PM PDT 24 |
Aug 17 06:00:05 PM PDT 24 |
53652795 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3573331320 |
|
|
Aug 17 06:00:21 PM PDT 24 |
Aug 17 06:00:25 PM PDT 24 |
40330070 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1316050436 |
|
|
Aug 17 06:00:31 PM PDT 24 |
Aug 17 06:00:33 PM PDT 24 |
239994655 ps |
| T1002 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3535943463 |
|
|
Aug 17 05:59:46 PM PDT 24 |
Aug 17 05:59:47 PM PDT 24 |
26065397 ps |
| T1003 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4010497027 |
|
|
Aug 17 05:59:47 PM PDT 24 |
Aug 17 05:59:48 PM PDT 24 |
61133497 ps |
| T148 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1333948780 |
|
|
Aug 17 06:00:31 PM PDT 24 |
Aug 17 06:00:33 PM PDT 24 |
542378899 ps |
| T1004 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3973454100 |
|
|
Aug 17 06:00:06 PM PDT 24 |
Aug 17 06:00:07 PM PDT 24 |
47390225 ps |
| T1005 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3103822871 |
|
|
Aug 17 06:00:13 PM PDT 24 |
Aug 17 06:00:15 PM PDT 24 |
443173631 ps |
| T1006 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3685459955 |
|
|
Aug 17 05:59:34 PM PDT 24 |
Aug 17 05:59:34 PM PDT 24 |
18536481 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.650027725 |
|
|
Aug 17 05:59:56 PM PDT 24 |
Aug 17 06:00:53 PM PDT 24 |
17156668205 ps |
| T1007 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2224002929 |
|
|
Aug 17 06:00:18 PM PDT 24 |
Aug 17 06:00:22 PM PDT 24 |
700684023 ps |
| T1008 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.140009874 |
|
|
Aug 17 06:00:22 PM PDT 24 |
Aug 17 06:00:22 PM PDT 24 |
73835889 ps |
| T1009 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3537396012 |
|
|
Aug 17 06:00:21 PM PDT 24 |
Aug 17 06:00:23 PM PDT 24 |
337564728 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1816623789 |
|
|
Aug 17 06:00:22 PM PDT 24 |
Aug 17 06:00:49 PM PDT 24 |
4337696335 ps |
| T99 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3924880150 |
|
|
Aug 17 06:00:23 PM PDT 24 |
Aug 17 06:00:53 PM PDT 24 |
14783674750 ps |