Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16266741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162762345

1

T1

589824

T2

3339

T3

169326

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88267934	1			T1	294912		T2	32171		T3	92536
values[0x0]	43767264	1			T1	147151		T2	10319		T3	45260
values[0x1]	46993888	1			T1	147761		T2	22191		T3	48565

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8276012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

170753074

1

T1

589824

T2

29397

T3

177882

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	623178	1			T1	2333		T2	257		T3	719
valid_sources[0x01]	605003	1			T1	2371		T2	235		T3	733
valid_sources[0x02]	583727	1			T1	2413		T2	279		T3	698
valid_sources[0x03]	594686	1			T1	2282		T2	234		T3	710
valid_sources[0x04]	583635	1			T1	2284		T2	276		T3	721
valid_sources[0x05]	584855	1			T1	2329		T2	254		T3	736
valid_sources[0x06]	632548	1			T1	2260		T2	232		T3	697
valid_sources[0x07]	599606	1			T1	2287		T2	274		T3	704
valid_sources[0x08]	609668	1			T1	2244		T2	226		T3	730
valid_sources[0x09]	1567489	1			T1	2358		T2	243		T3	734
valid_sources[0x0a]	650807	1			T1	2178		T2	247		T3	761
valid_sources[0x0b]	615053	1			T1	2311		T2	277		T3	750
valid_sources[0x0c]	623000	1			T1	2413		T2	241		T3	671
valid_sources[0x0d]	581077	1			T1	2284		T2	263		T3	690
valid_sources[0x0e]	623143	1			T1	2182		T2	257		T3	707
valid_sources[0x0f]	665714	1			T1	2376		T2	235		T3	756
valid_sources[0x10]	581545	1			T1	2289		T2	223		T3	674
valid_sources[0x11]	702425	1			T1	2420		T2	230		T3	693
valid_sources[0x12]	608012	1			T1	2268		T2	255		T3	747
valid_sources[0x13]	607649	1			T1	2358		T2	247		T3	743
valid_sources[0x14]	585803	1			T1	2326		T2	292		T3	677
valid_sources[0x15]	587339	1			T1	2260		T2	237		T3	807
valid_sources[0x16]	615131	1			T1	2276		T2	251		T3	723
valid_sources[0x17]	625258	1			T1	2266		T2	241		T3	739
valid_sources[0x18]	673315	1			T1	2234		T2	241		T3	688
valid_sources[0x19]	586151	1			T1	2276		T2	263		T3	692
valid_sources[0x1a]	595504	1			T1	2199		T2	248		T3	686
valid_sources[0x1b]	632028	1			T1	2267		T2	228		T3	730
valid_sources[0x1c]	568760	1			T1	2257		T2	286		T3	736
valid_sources[0x1d]	570688	1			T1	2329		T2	227		T3	702
valid_sources[0x1e]	614285	1			T1	2264		T2	226		T3	765
valid_sources[0x1f]	648917	1			T1	2254		T2	309		T3	741
valid_sources[0x20]	581528	1			T1	2354		T2	302		T3	706
valid_sources[0x21]	715485	1			T1	2211		T2	221		T3	707
valid_sources[0x22]	672958	1			T1	2215		T2	244		T3	679
valid_sources[0x23]	584799	1			T1	2324		T2	285		T3	705
valid_sources[0x24]	626369	1			T1	2354		T2	240		T3	801
valid_sources[0x25]	569678	1			T1	2253		T2	256		T3	754
valid_sources[0x26]	631675	1			T1	2298		T2	232		T3	813
valid_sources[0x27]	614141	1			T1	2174		T2	246		T3	670
valid_sources[0x28]	1038699	1			T1	2290		T2	247		T3	732
valid_sources[0x29]	619209	1			T1	2301		T2	246		T3	664
valid_sources[0x2a]	696558	1			T1	2292		T2	269		T3	735
valid_sources[0x2b]	1540957	1			T1	2447		T2	261		T3	639
valid_sources[0x2c]	1857601	1			T1	2255		T2	268		T3	772
valid_sources[0x2d]	589114	1			T1	2332		T2	229		T3	739
valid_sources[0x2e]	577686	1			T1	2326		T2	249		T3	734
valid_sources[0x2f]	592916	1			T1	2348		T2	251		T3	709
valid_sources[0x30]	611588	1			T1	2308		T2	261		T3	725
valid_sources[0x31]	633886	1			T1	2256		T2	232		T3	752
valid_sources[0x32]	584219	1			T1	2252		T2	235		T3	779
valid_sources[0x33]	574801	1			T1	2457		T2	253		T3	727
valid_sources[0x34]	596740	1			T1	2366		T2	257		T3	669
valid_sources[0x35]	576070	1			T1	2333		T2	266		T3	690
valid_sources[0x36]	601189	1			T1	2267		T2	261		T3	746
valid_sources[0x37]	581873	1			T1	2358		T2	265		T3	765
valid_sources[0x38]	630495	1			T1	2304		T2	240		T3	672
valid_sources[0x39]	626459	1			T1	2333		T2	246		T3	782
valid_sources[0x3a]	572215	1			T1	2234		T2	263		T3	781
valid_sources[0x3b]	929551	1			T1	2312		T2	266		T3	752
valid_sources[0x3c]	580587	1			T1	2300		T2	256		T3	791
valid_sources[0x3d]	1216241	1			T1	2284		T2	237		T3	758
valid_sources[0x3e]	570135	1			T1	2397		T2	231		T3	694
valid_sources[0x3f]	594714	1			T1	2337		T2	217		T3	692
valid_sources[0x40]	636319	1			T1	2316		T2	272		T3	686
valid_sources[0x41]	632055	1			T1	2396		T2	267		T3	719
valid_sources[0x42]	629582	1			T1	2265		T2	242		T3	779
valid_sources[0x43]	609716	1			T1	2230		T2	251		T3	771
valid_sources[0x44]	652012	1			T1	2357		T2	249		T3	707
valid_sources[0x45]	619203	1			T1	2308		T2	238		T3	729
valid_sources[0x46]	1992011	1			T1	2347		T2	232		T3	799
valid_sources[0x47]	601760	1			T1	2273		T2	260		T3	747
valid_sources[0x48]	577141	1			T1	2384		T2	241		T3	729
valid_sources[0x49]	2173162	1			T1	2369		T2	272		T3	679
valid_sources[0x4a]	617397	1			T1	2260		T2	258		T3	729
valid_sources[0x4b]	589122	1			T1	2256		T2	273		T3	738
valid_sources[0x4c]	578361	1			T1	2167		T2	260		T3	786
valid_sources[0x4d]	620867	1			T1	2320		T2	242		T3	733
valid_sources[0x4e]	623242	1			T1	2400		T2	227		T3	735
valid_sources[0x4f]	605949	1			T1	2299		T2	259		T3	738
valid_sources[0x50]	1083550	1			T1	2346		T2	248		T3	725
valid_sources[0x51]	612918	1			T1	2356		T2	246		T3	737
valid_sources[0x52]	620431	1			T1	2334		T2	269		T3	816
valid_sources[0x53]	600370	1			T1	2305		T2	235		T3	722
valid_sources[0x54]	612045	1			T1	2316		T2	295		T3	731
valid_sources[0x55]	681656	1			T1	2376		T2	243		T3	689
valid_sources[0x56]	854667	1			T1	2282		T2	275		T3	712
valid_sources[0x57]	585476	1			T1	2379		T2	243		T3	692
valid_sources[0x58]	572467	1			T1	2316		T2	256		T3	764
valid_sources[0x59]	693771	1			T1	2346		T2	273		T3	730
valid_sources[0x5a]	599173	1			T1	2178		T2	253		T3	702
valid_sources[0x5b]	578105	1			T1	2358		T2	261		T3	717
valid_sources[0x5c]	656674	1			T1	2258		T2	271		T3	710
valid_sources[0x5d]	584747	1			T1	2251		T2	241		T3	756
valid_sources[0x5e]	604473	1			T1	2375		T2	217		T3	719
valid_sources[0x5f]	589286	1			T1	2322		T2	254		T3	723
valid_sources[0x60]	616182	1			T1	2388		T2	259		T3	723
valid_sources[0x61]	609076	1			T1	2373		T2	234		T3	743
valid_sources[0x62]	588230	1			T1	2334		T2	247		T3	759
valid_sources[0x63]	633294	1			T1	2289		T2	256		T3	744
valid_sources[0x64]	656179	1			T1	2285		T2	257		T3	671
valid_sources[0x65]	678580	1			T1	2319		T2	270		T3	699
valid_sources[0x66]	776773	1			T1	2369		T2	249		T3	664
valid_sources[0x67]	668481	1			T1	2291		T2	269		T3	737
valid_sources[0x68]	677844	1			T1	2295		T2	241		T3	755
valid_sources[0x69]	1618993	1			T1	2269		T2	254		T3	708
valid_sources[0x6a]	576429	1			T1	2281		T2	256		T3	730
valid_sources[0x6b]	609360	1			T1	2223		T2	231		T3	726
valid_sources[0x6c]	585714	1			T1	2204		T2	271		T3	730
valid_sources[0x6d]	596901	1			T1	2304		T2	231		T3	687
valid_sources[0x6e]	625348	1			T1	2243		T2	240		T3	765
valid_sources[0x6f]	640500	1			T1	2370		T2	245		T3	732
valid_sources[0x70]	577594	1			T1	2326		T2	236		T3	730
valid_sources[0x71]	608612	1			T1	2384		T2	255		T3	690
valid_sources[0x72]	1707333	1			T1	2356		T2	242		T3	743
valid_sources[0x73]	575662	1			T1	2325		T2	227		T3	723
valid_sources[0x74]	581383	1			T1	2156		T2	248		T3	751
valid_sources[0x75]	586762	1			T1	2236		T2	235		T3	712
valid_sources[0x76]	998049	1			T1	2357		T2	239		T3	712
valid_sources[0x77]	1927743	1			T1	2382		T2	253		T3	771
valid_sources[0x78]	678264	1			T1	2406		T2	267		T3	733
valid_sources[0x79]	860171	1			T1	2364		T2	262		T3	721
valid_sources[0x7a]	616869	1			T1	2300		T2	254		T3	733
valid_sources[0x7b]	588767	1			T1	2271		T2	261		T3	668
valid_sources[0x7c]	642546	1			T1	2306		T2	269		T3	760
valid_sources[0x7d]	677385	1			T1	2259		T2	239		T3	715
valid_sources[0x7e]	2116620	1			T1	2300		T2	256		T3	706
valid_sources[0x7f]	673366	1			T1	2352		T2	246		T3	778
valid_sources[0x80]	598342	1			T1	2406		T2	251		T3	696

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80092515

1

T1

294912

T2

258

T3

83980

values[0x0]

all_enables

biggest_size

41337767

1

T1

147151

T2

1550

T3

42679

values[0x1]

all_enables

biggest_size

41332063

1

T1

147761

T2

1531

T3

42667

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

146205

1

T1

1

T2

2

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52247	1			T3	26		T4	34		T5	35
values[0x0]	66782	1			T1	2		T2	1		T3	50
values[0x1]	71139	1			T1	7		T2	3		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155952

1

T1

3

T2

2

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	703	1			T23	4		T63	1		T25	5
valid_sources[0x01]	1126	1			T23	2		T13	1		T63	1
valid_sources[0x02]	938	1			T23	3		T46	1		T51	108
valid_sources[0x03]	673	1			T23	7		T145	3		T140	4
valid_sources[0x04]	847	1			T23	6		T69	1		T139	1
valid_sources[0x05]	558	1			T4	1		T5	1		T10	11
valid_sources[0x06]	728	1			T9	1		T10	1		T11	3
valid_sources[0x07]	1300	1			T42	1		T23	5		T86	8
valid_sources[0x08]	617	1			T23	6		T63	2		T20	1
valid_sources[0x09]	708	1			T3	6		T11	1		T42	1
valid_sources[0x0a]	595	1			T4	1		T5	1		T10	2
valid_sources[0x0b]	1301	1			T4	1		T23	4		T24	695
valid_sources[0x0c]	730	1			T23	9		T121	1		T25	39
valid_sources[0x0d]	653	1			T5	1		T11	2		T41	4
valid_sources[0x0e]	940	1			T9	1		T23	12		T123	1
valid_sources[0x0f]	934	1			T11	1		T42	2		T23	10
valid_sources[0x10]	725	1			T42	2		T23	6		T24	6
valid_sources[0x11]	797	1			T23	4		T86	2		T24	77
valid_sources[0x12]	640	1			T4	4		T8	1		T42	1
valid_sources[0x13]	773	1			T11	1		T23	9		T59	13
valid_sources[0x14]	683	1			T2	1		T3	12		T4	1
valid_sources[0x15]	944	1			T41	3		T23	7		T25	2
valid_sources[0x16]	566	1			T4	1		T5	2		T23	4
valid_sources[0x17]	542	1			T9	3		T23	6		T46	1
valid_sources[0x18]	683	1			T5	1		T11	2		T23	9
valid_sources[0x19]	719	1			T5	1		T10	2		T11	1
valid_sources[0x1a]	575	1			T3	7		T23	9		T46	1
valid_sources[0x1b]	762	1			T5	2		T42	1		T23	7
valid_sources[0x1c]	925	1			T5	1		T42	2		T23	8
valid_sources[0x1d]	947	1			T23	5		T121	1		T57	2
valid_sources[0x1e]	743	1			T4	1		T23	6		T72	1
valid_sources[0x1f]	677	1			T23	1		T25	2		T51	97
valid_sources[0x20]	771	1			T23	5		T101	3		T79	11
valid_sources[0x21]	596	1			T23	7		T56	4		T79	14
valid_sources[0x22]	921	1			T5	1		T42	1		T23	6
valid_sources[0x23]	1293	1			T1	2		T42	6		T23	7
valid_sources[0x24]	777	1			T11	1		T23	7		T63	1
valid_sources[0x25]	634	1			T5	1		T23	7		T45	8
valid_sources[0x26]	671	1			T5	1		T23	6		T119	1
valid_sources[0x27]	722	1			T3	5		T11	4		T40	5
valid_sources[0x28]	907	1			T23	2		T24	1		T25	2
valid_sources[0x29]	904	1			T23	10		T140	8		T51	167
valid_sources[0x2a]	685	1			T11	2		T42	2		T23	6
valid_sources[0x2b]	587	1			T41	4		T42	3		T23	10
valid_sources[0x2c]	650	1			T3	3		T11	1		T23	4
valid_sources[0x2d]	727	1			T2	2		T23	2		T63	2
valid_sources[0x2e]	555	1			T5	1		T23	3		T20	2
valid_sources[0x2f]	681	1			T11	1		T23	4		T19	25
valid_sources[0x30]	581	1			T11	1		T23	8		T19	3
valid_sources[0x31]	624	1			T4	1		T11	1		T42	1
valid_sources[0x32]	674	1			T9	1		T10	7		T23	6
valid_sources[0x33]	810	1			T3	3		T42	1		T23	3
valid_sources[0x34]	712	1			T4	1		T5	1		T23	2
valid_sources[0x35]	1105	1			T11	1		T23	2		T24	10
valid_sources[0x36]	630	1			T4	2		T42	1		T23	8
valid_sources[0x37]	1044	1			T11	2		T23	3		T84	1
valid_sources[0x38]	604	1			T23	5		T119	2		T112	1
valid_sources[0x39]	764	1			T4	2		T5	1		T11	1
valid_sources[0x3a]	632	1			T4	1		T23	8		T123	1
valid_sources[0x3b]	667	1			T42	1		T23	3		T45	2
valid_sources[0x3c]	722	1			T41	2		T23	6		T46	2
valid_sources[0x3d]	554	1			T42	1		T23	5		T123	1
valid_sources[0x3e]	731	1			T10	1		T11	1		T42	2
valid_sources[0x3f]	876	1			T23	6		T46	1		T57	1
valid_sources[0x40]	726	1			T42	4		T23	10		T46	1
valid_sources[0x41]	573	1			T23	5		T50	1		T51	4
valid_sources[0x42]	686	1			T3	6		T11	3		T23	4
valid_sources[0x43]	811	1			T23	3		T123	3		T56	2
valid_sources[0x44]	714	1			T5	1		T23	5		T72	2
valid_sources[0x45]	1163	1			T4	1		T23	5		T63	3
valid_sources[0x46]	586	1			T4	1		T5	1		T11	1
valid_sources[0x47]	947	1			T3	7		T11	2		T23	6
valid_sources[0x48]	883	1			T5	1		T23	2		T72	6
valid_sources[0x49]	578	1			T23	8		T6	2		T72	7
valid_sources[0x4a]	805	1			T42	2		T23	5		T123	4
valid_sources[0x4b]	679	1			T11	1		T23	3		T72	8
valid_sources[0x4c]	698	1			T9	3		T10	1		T23	6
valid_sources[0x4d]	655	1			T1	1		T5	1		T23	5
valid_sources[0x4e]	1004	1			T5	2		T23	8		T63	1
valid_sources[0x4f]	526	1			T3	3		T23	6		T51	1
valid_sources[0x50]	672	1			T5	4		T42	2		T23	6
valid_sources[0x51]	514	1			T23	2		T55	1		T56	4
valid_sources[0x52]	672	1			T4	1		T23	5		T123	1
valid_sources[0x53]	543	1			T23	12		T24	2		T25	20
valid_sources[0x54]	764	1			T5	1		T9	1		T23	2
valid_sources[0x55]	607	1			T23	6		T123	1		T121	2
valid_sources[0x56]	920	1			T10	2		T23	5		T24	4
valid_sources[0x57]	699	1			T4	2		T11	1		T23	2
valid_sources[0x58]	560	1			T23	11		T56	2		T146	1
valid_sources[0x59]	977	1			T3	1		T23	4		T123	1
valid_sources[0x5a]	905	1			T23	7		T44	1		T124	2
valid_sources[0x5b]	527	1			T23	4		T24	1		T140	1
valid_sources[0x5c]	650	1			T42	4		T23	6		T84	1
valid_sources[0x5d]	793	1			T10	4		T42	1		T23	3
valid_sources[0x5e]	548	1			T23	3		T139	2		T51	2
valid_sources[0x5f]	862	1			T11	1		T23	4		T145	1
valid_sources[0x60]	844	1			T5	1		T23	8		T46	1
valid_sources[0x61]	638	1			T23	10		T56	3		T146	1
valid_sources[0x62]	666	1			T4	1		T23	5		T145	1
valid_sources[0x63]	623	1			T23	11		T13	1		T123	2
valid_sources[0x64]	545	1			T23	6		T56	1		T101	1
valid_sources[0x65]	643	1			T3	5		T10	2		T23	7
valid_sources[0x66]	808	1			T23	11		T24	108		T147	4
valid_sources[0x67]	562	1			T11	4		T23	3		T148	3
valid_sources[0x68]	820	1			T3	3		T4	2		T23	4
valid_sources[0x69]	738	1			T3	5		T4	2		T42	1
valid_sources[0x6a]	719	1			T4	2		T23	7		T6	3
valid_sources[0x6b]	766	1			T4	1		T5	1		T23	3
valid_sources[0x6c]	592	1			T3	5		T9	2		T10	2
valid_sources[0x6d]	626	1			T42	2		T23	3		T145	1
valid_sources[0x6e]	635	1			T5	1		T9	2		T11	1
valid_sources[0x6f]	840	1			T23	6		T149	1		T119	2
valid_sources[0x70]	703	1			T23	1		T13	1		T24	99
valid_sources[0x71]	783	1			T4	1		T5	1		T11	1
valid_sources[0x72]	684	1			T42	1		T23	4		T12	1
valid_sources[0x73]	1184	1			T4	1		T5	1		T23	7
valid_sources[0x74]	463	1			T23	3		T79	16		T150	1
valid_sources[0x75]	947	1			T11	1		T42	1		T23	2
valid_sources[0x76]	888	1			T11	2		T42	3		T23	4
valid_sources[0x77]	1156	1			T23	7		T6	3		T72	3
valid_sources[0x78]	953	1			T23	4		T47	89		T51	90
valid_sources[0x79]	585	1			T9	1		T42	1		T23	6
valid_sources[0x7a]	792	1			T5	1		T23	7		T113	3
valid_sources[0x7b]	818	1			T4	1		T11	1		T23	3
valid_sources[0x7c]	728	1			T23	2		T6	3		T110	1
valid_sources[0x7d]	626	1			T42	1		T23	5		T24	4
valid_sources[0x7e]	541	1			T42	2		T23	6		T55	1
valid_sources[0x7f]	558	1			T23	4		T63	1		T43	29
valid_sources[0x80]	1109	1			T23	3		T72	1		T119	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39588

1

T3

14

T4

15

T5

23

values[0x0]

all_enables

biggest_size

54839

1

T2

1

T3

17

T4

7

values[0x1]

all_enables

biggest_size

51778

1

T1

1

T2

1

T3

6