Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16136925

1

T2

61342

T3

14608

T4

109

full_word

159481329

1

T1

589824

T2

3339

T3

145255

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	175617954	1			T1	589824		T2	64681		T3	159863
auto[TlIntgErrCmd]	85	1			T73	4		T74	1		T75	7
auto[TlIntgErrData]	125	1			T73	10		T74	6		T75	8
auto[TlIntgErrBoth]	90	1			T73	6		T74	3		T75	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84781074

1

T1

294912

T2

32171

T3

66038

auto[1]

90837180

1

T1

294912

T2

32510

T3

93825

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7894806	1			T2	31913		T3	6129		T4	55
auto[TlIntgErrNone]	partial	auto[1]	8241836	1			T2	29429		T3	8479		T4	54
auto[TlIntgErrNone]	full_word	auto[0]	76886139	1			T1	294912		T2	258		T3	59909
auto[TlIntgErrNone]	full_word	auto[1]	82595173	1			T1	294912		T2	3081		T3	85346
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T73	2		T74	1		T75	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T73	2		T75	2		T125	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T75	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T75	1		T129	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T73	4		T74	2		T75	3
auto[TlIntgErrData]	partial	auto[1]	69	1			T73	6		T74	4		T75	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T133	1		T134	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T135	1		T136	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T73	3		T74	3		T75	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T73	2		T75	3		T125	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T138	1		T132	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T73	1		T133	1		T135	1