Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	705697	1			T2	4348		T5	26		T40	8233
auto[1]	11043300	1			T2	4721		T3	4055		T4	612
auto[2]	526208	1			T2	4121		T5	37		T40	7464
auto[3]	10757785	1			T2	4758		T3	3492		T4	590

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14700537	1			T2	9		T3	6219		T4	1020
auto[1]	2160877	1			T2	402		T3	648		T4	90
auto[2]	2199457	1			T2	718		T3	615		T4	89
auto[3]	3972119	1			T2	16819		T3	65		T4	3

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10091140

1

T2

17947

T3

7547

T4

1202

auto[1]

12941850

1

T2

1

T41

2

T71

115463

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	319839	1			T2	1		T5	16		T40	6787
auto[0]	auto[0]	auto[1]	32843	1			T2	25		T5	4		T40	721
auto[0]	auto[0]	auto[2]	32868	1			T2	25		T5	5		T40	662
auto[0]	auto[0]	auto[3]	37758	1			T2	4297		T5	1		T40	63
auto[0]	auto[1]	auto[0]	3710579	1			T2	3		T3	3335		T4	522
auto[0]	auto[1]	auto[1]	385942	1			T2	39		T3	329		T4	42
auto[0]	auto[1]	auto[2]	393468	1			T2	245		T3	358		T4	47
auto[0]	auto[1]	auto[3]	303960	1			T2	4433		T3	33		T4	1
auto[0]	auto[2]	auto[0]	225487	1			T5	30		T40	6296		T45	752
auto[0]	auto[2]	auto[1]	24701	1			T2	241		T5	4		T40	663
auto[0]	auto[2]	auto[2]	26122	1			T2	27		T5	3		T40	474
auto[0]	auto[2]	auto[3]	27996	1			T2	3853		T40	31		T84	6
auto[0]	auto[3]	auto[0]	3529146	1			T2	5		T3	2884		T4	498
auto[0]	auto[3]	auto[1]	373486	1			T2	97		T3	319		T4	48
auto[0]	auto[3]	auto[2]	387349	1			T2	421		T3	257		T4	42
auto[0]	auto[3]	auto[3]	279596	1			T2	4235		T3	32		T4	2
auto[1]	auto[0]	auto[0]	9384	1			T60	889		T45	1		T69	146
auto[1]	auto[0]	auto[1]	42079	1			T60	3969		T69	669		T110	527
auto[1]	auto[0]	auto[2]	41747	1			T60	3862		T69	634		T110	513
auto[1]	auto[0]	auto[3]	189179	1			T60	18109		T69	3032		T110	2067
auto[1]	auto[1]	auto[0]	3452934	1			T41	2		T71	47656		T72	4
auto[1]	auto[1]	auto[1]	648294	1			T71	4734		T60	4058		T68	7167
auto[1]	auto[1]	auto[2]	641366	1			T71	4816		T60	664		T68	7105
auto[1]	auto[1]	auto[3]	1506757	1			T2	1		T71	510		T60	18127
auto[1]	auto[2]	auto[0]	5933	1			T60	852		T46	1		T124	1
auto[1]	auto[2]	auto[1]	26385	1			T60	3748		T141	2311		T142	2938
auto[1]	auto[2]	auto[2]	34814	1			T60	2791		T69	608		T110	436
auto[1]	auto[2]	auto[3]	154770	1			T60	12062		T69	2719		T110	1960
auto[1]	auto[3]	auto[0]	3447235	1			T71	47648		T72	3		T86	1
auto[1]	auto[3]	auto[1]	627147	1			T71	4757		T72	1		T60	449
auto[1]	auto[3]	auto[2]	641723	1			T71	4847		T60	2783		T68	7143
auto[1]	auto[3]	auto[3]	1472103	1			T71	495		T60	12308		T68	708