Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1059888588	205620	0	0
ctrl_regwen_rd_A	1059888588	6256	0	0
exec_rd_A	1059888588	5968	0	0
exec_regwen_rd_A	1059888588	6137	0	0
readback_rd_A	1059888588	4349	0	0
readback_regwen_rd_A	1059888588	3702	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059888588	205620	0	0
T6	438705	0	0	0
T12	1164	0	0	0
T13	900	0	0	0
T19	683181	0	0	0
T23	45613	1933	0	0
T24	0	2306	0	0
T25	0	6749	0	0
T51	0	5411	0	0
T65	0	3839	0	0
T71	259762	0	0	0
T72	611622	0	0	0
T79	0	6055	0	0
T80	0	3309	0	0
T81	0	2967	0	0
T82	0	4805	0	0
T83	0	1753	0	0
T84	739167	0	0	0
T85	76362	0	0	0
T86	930509	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059888588	6256	0	0
T20	219418	0	0	0
T24	95084	222	0	0
T28	33594	0	0	0
T35	0	59	0	0
T46	246024	0	0	0
T47	118867	0	0	0
T51	0	368	0	0
T53	0	579	0	0
T80	0	174	0	0
T83	0	62	0	0
T110	114927	0	0	0
T115	0	463	0	0
T116	0	207	0	0
T117	0	370	0	0
T118	0	99	0	0
T119	674058	0	0	0
T120	77139	0	0	0
T121	728964	0	0	0
T122	52387	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059888588	5968	0	0
T20	219418	0	0	0
T24	95084	195	0	0
T28	33594	0	0	0
T35	0	41	0	0
T46	246024	0	0	0
T47	118867	0	0	0
T51	0	476	0	0
T53	0	514	0	0
T80	0	230	0	0
T83	0	28	0	0
T110	114927	0	0	0
T115	0	391	0	0
T116	0	280	0	0
T117	0	313	0	0
T118	0	128	0	0
T119	674058	0	0	0
T120	77139	0	0	0
T121	728964	0	0	0
T122	52387	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059888588	6137	0	0
T20	219418	0	0	0
T24	95084	161	0	0
T28	33594	0	0	0
T35	0	49	0	0
T46	246024	0	0	0
T47	118867	0	0	0
T51	0	458	0	0
T53	0	544	0	0
T80	0	222	0	0
T83	0	128	0	0
T110	114927	0	0	0
T115	0	485	0	0
T116	0	211	0	0
T117	0	345	0	0
T118	0	112	0	0
T119	674058	0	0	0
T120	77139	0	0	0
T121	728964	0	0	0
T122	52387	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059888588	4349	0	0
T20	219418	0	0	0
T24	95084	281	0	0
T28	33594	0	0	0
T35	0	35	0	0
T46	246024	0	0	0
T47	118867	0	0	0
T51	0	442	0	0
T53	0	597	0	0
T80	0	180	0	0
T83	0	66	0	0
T110	114927	0	0	0
T115	0	393	0	0
T116	0	249	0	0
T117	0	278	0	0
T118	0	159	0	0
T119	674058	0	0	0
T120	77139	0	0	0
T121	728964	0	0	0
T122	52387	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059888588	3702	0	0
T20	219418	0	0	0
T24	95084	159	0	0
T28	33594	0	0	0
T35	0	49	0	0
T46	246024	0	0	0
T47	118867	0	0	0
T51	0	417	0	0
T53	0	399	0	0
T80	0	199	0	0
T83	0	32	0	0
T110	114927	0	0	0
T115	0	349	0	0
T116	0	191	0	0
T117	0	227	0	0
T118	0	74	0	0
T119	674058	0	0	0
T120	77139	0	0	0
T121	728964	0	0	0
T122	52387	0	0	0