Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16161049

1

T1

196

T2

6820

T4

36

full_word

155442079

1

T1

2104

T2

1491

T3

8702

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	171602838	1			T1	2300		T2	8311		T3	8702
auto[TlIntgErrCmd]	94	1			T64	2		T65	4		T66	3
auto[TlIntgErrData]	93	1			T64	4		T65	4		T66	1
auto[TlIntgErrBoth]	103	1			T64	4		T65	2		T66	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82713478

1

T1

1126

T2

4145

T3

4353

auto[1]

88889650

1

T1

1174

T2

4166

T3

4349

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7915348	1			T1	94		T2	3407		T4	20
auto[TlIntgErrNone]	partial	auto[1]	8245438	1			T1	102		T2	3413		T4	16
auto[TlIntgErrNone]	full_word	auto[0]	74798018	1			T1	1032		T2	738		T3	4353
auto[TlIntgErrNone]	full_word	auto[1]	80644034	1			T1	1072		T2	753		T3	4349
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T65	1		T129	1		T130	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T64	2		T65	2		T66	3
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T65	1		T131	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T64	1		T66	1		T129	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T64	3		T65	3		T130	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T130	1		T133	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T65	1		T133	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T64	1		T65	1		T66	4
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T64	3		T65	1		T66	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T136	1		T137	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T66	1		T130	1		T132	1