Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	679654	1			T32	1218		T35	154		T59	45
auto[1]	10925039	1			T1	9		T3	4351		T4	149
auto[2]	482262	1			T8	1		T32	1124		T6	1
auto[3]	10660862	1			T1	8		T3	4348		T4	166

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14302617	1			T1	8		T3	8699		T4	256
auto[1]	2103719	1			T1	5		T4	27		T10	780
auto[2]	2165407	1			T1	4		T4	31		T10	767
auto[3]	4176074	1			T4	1		T10	174		T12	955

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10126241

1

T1

17

T3

8699

T4

315

auto[1]

12621576

1

T12

112903

T31

1

T33

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	262858	1			T32	1006		T35	137		T59	37
auto[0]	auto[0]	auto[1]	27668	1			T32	99		T35	11		T59	4
auto[0]	auto[0]	auto[2]	27497	1			T32	100		T35	6		T59	4
auto[0]	auto[0]	auto[3]	75142	1			T32	13		T124	109		T36	10
auto[0]	auto[1]	auto[0]	3646206	1			T1	4		T3	4351		T4	120
auto[0]	auto[1]	auto[1]	370380	1			T1	3		T4	11		T10	384
auto[0]	auto[1]	auto[2]	400397	1			T1	2		T4	17		T10	371
auto[0]	auto[1]	auto[3]	420683	1			T4	1		T10	89		T8	1
auto[0]	auto[2]	auto[0]	159732	1			T32	960		T6	1		T25	2
auto[0]	auto[2]	auto[1]	21411	1			T32	91		T25	1		T36	71
auto[0]	auto[2]	auto[2]	23880	1			T32	67		T35	77		T59	16
auto[0]	auto[2]	auto[3]	56547	1			T8	1		T32	6		T35	7
auto[0]	auto[3]	auto[0]	3483402	1			T1	4		T3	4348		T4	136
auto[0]	auto[3]	auto[1]	378036	1			T1	2		T4	16		T10	396
auto[0]	auto[3]	auto[2]	390661	1			T1	2		T4	14		T10	396
auto[0]	auto[3]	auto[3]	381741	1			T10	85		T8	3		T32	11
auto[1]	auto[0]	auto[0]	9610	1			T111	873		T113	308		T114	93
auto[1]	auto[0]	auto[1]	42649	1			T111	4152		T113	1382		T114	359
auto[1]	auto[0]	auto[2]	42717	1			T111	4044		T113	1344		T114	400
auto[1]	auto[0]	auto[3]	191513	1			T111	18075		T113	6184		T114	1848
auto[1]	auto[1]	auto[0]	3368672	1			T12	46570		T62	86685		T109	54003
auto[1]	auto[1]	auto[1]	629878	1			T12	4584		T62	8516		T109	5411
auto[1]	auto[1]	auto[2]	624013	1			T12	4643		T62	8635		T109	5490
auto[1]	auto[1]	auto[3]	1464810	1			T12	479		T62	880		T109	549
auto[1]	auto[2]	auto[0]	5747	1			T36	1		T111	811		T113	210
auto[1]	auto[2]	auto[1]	26252	1			T111	3769		T113	850		T149	3980
auto[1]	auto[2]	auto[2]	34178	1			T111	2790		T113	1297		T114	324
auto[1]	auto[2]	auto[3]	154515	1			T111	12181		T113	6015		T114	1625
auto[1]	auto[3]	auto[0]	3366390	1			T12	46807		T31	1		T62	87202
auto[1]	auto[3]	auto[1]	607445	1			T12	4666		T62	8680		T109	5419
auto[1]	auto[3]	auto[2]	622064	1			T12	4678		T62	8774		T109	5450
auto[1]	auto[3]	auto[3]	1431123	1			T12	476		T33	1		T62	838