Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1206675655	212048	0	0
ctrl_regwen_rd_A	1206675655	4855	0	0
exec_rd_A	1206675655	4160	0	0
exec_regwen_rd_A	1206675655	4355	0	0
readback_rd_A	1206675655	3599	0	0
readback_regwen_rd_A	1206675655	3149	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206675655	212048	0	0
T6	106469	0	0	0
T13	1069	0	0	0
T16	12751	0	0	0
T23	156087	5868	0	0
T24	0	4658	0	0
T25	0	3567	0	0
T27	34185	0	0	0
T31	71048	0	0	0
T32	132845	0	0	0
T33	157582	0	0	0
T34	77917	0	0	0
T35	555494	0	0	0
T48	0	2685	0	0
T51	0	9750	0	0
T63	0	2048	0	0
T70	0	1850	0	0
T71	0	2912	0	0
T72	0	3496	0	0
T73	0	2591	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206675655	4855	0	0
T25	110058	146	0	0
T36	116204	0	0	0
T50	0	335	0	0
T55	0	202	0	0
T63	0	172	0	0
T71	0	272	0	0
T83	101698	0	0	0
T89	95986	0	0	0
T109	349396	0	0	0
T119	0	144	0	0
T120	0	132	0	0
T121	0	336	0	0
T122	0	191	0	0
T123	0	107	0	0
T124	65511	0	0	0
T125	71384	0	0	0
T126	521529	0	0	0
T127	34852	0	0	0
T128	74276	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206675655	4160	0	0
T25	110058	119	0	0
T36	116204	0	0	0
T50	0	303	0	0
T55	0	191	0	0
T63	0	163	0	0
T71	0	195	0	0
T83	101698	0	0	0
T89	95986	0	0	0
T109	349396	0	0	0
T119	0	124	0	0
T120	0	62	0	0
T121	0	255	0	0
T122	0	167	0	0
T123	0	55	0	0
T124	65511	0	0	0
T125	71384	0	0	0
T126	521529	0	0	0
T127	34852	0	0	0
T128	74276	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206675655	4355	0	0
T25	110058	87	0	0
T36	116204	0	0	0
T50	0	317	0	0
T55	0	220	0	0
T63	0	171	0	0
T71	0	249	0	0
T83	101698	0	0	0
T89	95986	0	0	0
T109	349396	0	0	0
T119	0	169	0	0
T120	0	62	0	0
T121	0	257	0	0
T122	0	104	0	0
T123	0	77	0	0
T124	65511	0	0	0
T125	71384	0	0	0
T126	521529	0	0	0
T127	34852	0	0	0
T128	74276	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206675655	3599	0	0
T25	110058	90	0	0
T36	116204	0	0	0
T50	0	336	0	0
T55	0	254	0	0
T63	0	177	0	0
T71	0	270	0	0
T83	101698	0	0	0
T89	95986	0	0	0
T109	349396	0	0	0
T119	0	208	0	0
T120	0	80	0	0
T121	0	293	0	0
T122	0	144	0	0
T123	0	40	0	0
T124	65511	0	0	0
T125	71384	0	0	0
T126	521529	0	0	0
T127	34852	0	0	0
T128	74276	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206675655	3149	0	0
T25	110058	135	0	0
T36	116204	0	0	0
T50	0	264	0	0
T55	0	178	0	0
T63	0	152	0	0
T71	0	200	0	0
T83	101698	0	0	0
T89	95986	0	0	0
T109	349396	0	0	0
T119	0	135	0	0
T120	0	66	0	0
T121	0	244	0	0
T122	0	127	0	0
T123	0	68	0	0
T124	65511	0	0	0
T125	71384	0	0	0
T126	521529	0	0	0
T127	34852	0	0	0
T128	74276	0	0	0