Unified Coverage Report :: Module :: prim_buf

Module : prim_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf.u_secure_anchor_buf
tb.dut.u_prim_ram_1p_scr.u_read_en_buf
tb.dut.u_prim_ram_1p_scr.u_write_en_d_buf
tb.dut.u_prim_ram_1p_scr.u_addr_match_buf
tb.dut.u_prim_ram_1p_scr.u_intg_error
tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_req_d_buf
tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_write_d_buf
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[4].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[5].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[6].u_prim_buf
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[7].u_prim_buf

---

Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_read_en_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.53	98.11	100.00			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_write_en_d_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.53	98.11	100.00			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_addr_match_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.53	98.11	100.00			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_intg_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.53	98.11	100.00			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_req_d_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_prim_ram_1p_adv

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_write_d_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_prim_ram_1p_adv

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[4].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[5].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[6].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_buffs[0].gen_bits[7].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00