Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16774871

1

T1

273

T4

123

T5

41

full_word

167384654

1

T1

2830

T4

523

T5

462

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	184159195	1			T1	3103		T4	646		T5	503
auto[TlIntgErrCmd]	111	1			T60	10		T61	4		T62	8
auto[TlIntgErrData]	105	1			T60	7		T61	3		T62	5
auto[TlIntgErrBoth]	114	1			T60	3		T61	3		T62	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89015762

1

T1

1520

T4

308

T5

243

auto[1]

95143763

1

T1

1583

T4

338

T5

260

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8213588	1			T1	136		T4	55		T5	20
auto[TlIntgErrNone]	partial	auto[1]	8560979	1			T1	137		T4	68		T5	21
auto[TlIntgErrNone]	full_word	auto[0]	80802025	1			T1	1384		T4	253		T5	223
auto[TlIntgErrNone]	full_word	auto[1]	86582603	1			T1	1446		T4	270		T5	239
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T60	3		T61	3		T62	4
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T60	7		T61	1		T62	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T136	1		T142	1		T143	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T144	1		T145	1		T146	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T60	3		T61	2		T62	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T60	3		T62	4		T136	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T61	1		T138	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T60	1		T138	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T60	1		T61	1		T62	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T60	2		T61	2		T62	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T136	1		T138	2		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T136	1		T145	1		T146	1