Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	693729	1			T34	133		T28	421		T35	2
auto[1]	11088174	1			T4	307		T8	1304		T11	14
auto[2]	543509	1			T34	77		T28	170		T20	8
auto[3]	10824485	1			T4	337		T8	1214		T11	27

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14521179	1			T4	432		T8	2518		T11	35
auto[1]	2196164	1			T4	90		T11	3		T7	46
auto[2]	2247678	1			T4	99		T11	3		T7	39
auto[3]	4184876	1			T4	23		T7	5		T9	8

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9146542

1

T4

644

T8

2518

T11

41

auto[1]

14003355

1

T36

1

T29

2

T55

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	322106	1			T34	5		T28	338		T35	2
auto[0]	auto[0]	auto[1]	33596	1			T34	16		T28	37		T40	55
auto[0]	auto[0]	auto[2]	33599	1			T34	26		T28	44		T40	50
auto[0]	auto[0]	auto[3]	32319	1			T34	86		T28	2		T19	1
auto[0]	auto[1]	auto[0]	3346085	1			T4	212		T8	1304		T11	10
auto[0]	auto[1]	auto[1]	345714	1			T4	40		T11	2		T7	26
auto[0]	auto[1]	auto[2]	356438	1			T4	50		T11	2		T7	20
auto[0]	auto[1]	auto[3]	262513	1			T4	5		T7	2		T9	3
auto[0]	auto[2]	auto[0]	243866	1			T28	152		T19	9		T40	241
auto[0]	auto[2]	auto[1]	26412	1			T28	11		T19	1		T40	29
auto[0]	auto[2]	auto[2]	27427	1			T34	10		T28	6		T20	8
auto[0]	auto[2]	auto[3]	22443	1			T34	67		T28	1		T40	2
auto[0]	auto[3]	auto[0]	3173722	1			T4	220		T8	1214		T11	25
auto[0]	auto[3]	auto[1]	335068	1			T4	50		T11	1		T7	20
auto[0]	auto[3]	auto[2]	346525	1			T4	49		T11	1		T7	19
auto[0]	auto[3]	auto[3]	238709	1			T4	18		T7	3		T9	5
auto[1]	auto[0]	auto[0]	9120	1			T113	405		T155	187		T156	880
auto[1]	auto[0]	auto[1]	40026	1			T113	1594		T155	762		T156	3958
auto[1]	auto[0]	auto[2]	40573	1			T113	1597		T155	768		T156	3918
auto[1]	auto[0]	auto[3]	182390	1			T113	7293		T155	3523		T156	17376
auto[1]	auto[1]	auto[0]	3712951	1			T55	1		T157	1		T111	51268
auto[1]	auto[1]	auto[1]	710218	1			T111	4629		T112	7203		T113	1832
auto[1]	auto[1]	auto[2]	702400	1			T59	1		T84	1		T111	5099
auto[1]	auto[1]	auto[3]	1651855	1			T29	1		T59	1		T84	1
auto[1]	auto[2]	auto[0]	5065	1			T113	208		T158	1		T156	835
auto[1]	auto[2]	auto[1]	22626	1			T113	956		T156	3580		T159	1327
auto[1]	auto[2]	auto[2]	35131	1			T113	1689		T155	664		T156	3216
auto[1]	auto[2]	auto[3]	160539	1			T113	7693		T155	3165		T156	14573
auto[1]	auto[3]	auto[0]	3708264	1			T36	1		T29	1		T111	50950
auto[1]	auto[3]	auto[1]	682504	1			T111	5075		T112	7092		T113	371
auto[1]	auto[3]	auto[2]	705585	1			T111	4526		T112	7150		T113	2012
auto[1]	auto[3]	auto[3]	1634108	1			T84	1		T111	459		T112	720