Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1237796303	239652	0	0
ctrl_regwen_rd_A	1237796303	4401	0	0
exec_rd_A	1237796303	4032	0	0
exec_regwen_rd_A	1237796303	4599	0	0
readback_rd_A	1237796303	2777	0	0
readback_regwen_rd_A	1237796303	2512	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237796303	239652	0	0
T16	944	0	0	0
T18	14654	0	0	0
T24	347905	12697	0	0
T25	244766	13147	0	0
T26	0	6037	0	0
T28	245906	0	0	0
T35	70809	0	0	0
T42	692191	0	0	0
T52	0	7523	0	0
T59	160192	0	0	0
T66	0	1576	0	0
T67	0	632	0	0
T68	0	3308	0	0
T69	0	2172	0	0
T70	0	2857	0	0
T71	0	5619	0	0
T72	90129	0	0	0
T73	61962	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237796303	4401	0	0
T38	113927	0	0	0
T49	0	131	0	0
T67	11030	41	0	0
T70	0	276	0	0
T71	0	181	0	0
T121	0	127	0	0
T122	0	197	0	0
T123	0	111	0	0
T124	0	104	0	0
T125	0	175	0	0
T126	0	412	0	0
T127	537707	0	0	0
T128	775	0	0	0
T129	221575	0	0	0
T130	92005	0	0	0
T131	195175	0	0	0
T132	39374	0	0	0
T133	740846	0	0	0
T134	306995	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237796303	4032	0	0
T38	113927	0	0	0
T49	0	118	0	0
T67	11030	36	0	0
T70	0	220	0	0
T71	0	158	0	0
T121	0	117	0	0
T122	0	195	0	0
T123	0	96	0	0
T124	0	143	0	0
T125	0	181	0	0
T126	0	366	0	0
T127	537707	0	0	0
T128	775	0	0	0
T129	221575	0	0	0
T130	92005	0	0	0
T131	195175	0	0	0
T132	39374	0	0	0
T133	740846	0	0	0
T134	306995	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237796303	4599	0	0
T38	113927	0	0	0
T49	0	129	0	0
T67	11030	72	0	0
T70	0	243	0	0
T71	0	185	0	0
T121	0	113	0	0
T122	0	212	0	0
T123	0	134	0	0
T124	0	150	0	0
T125	0	224	0	0
T126	0	555	0	0
T127	537707	0	0	0
T128	775	0	0	0
T129	221575	0	0	0
T130	92005	0	0	0
T131	195175	0	0	0
T132	39374	0	0	0
T133	740846	0	0	0
T134	306995	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237796303	2777	0	0
T38	113927	0	0	0
T49	0	86	0	0
T67	11030	21	0	0
T70	0	232	0	0
T71	0	188	0	0
T121	0	100	0	0
T122	0	154	0	0
T123	0	119	0	0
T124	0	113	0	0
T125	0	146	0	0
T126	0	501	0	0
T127	537707	0	0	0
T128	775	0	0	0
T129	221575	0	0	0
T130	92005	0	0	0
T131	195175	0	0	0
T132	39374	0	0	0
T133	740846	0	0	0
T134	306995	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1237796303	2512	0	0
T38	113927	0	0	0
T49	0	91	0	0
T67	11030	23	0	0
T70	0	185	0	0
T71	0	195	0	0
T121	0	73	0	0
T122	0	145	0	0
T123	0	83	0	0
T124	0	151	0	0
T125	0	85	0	0
T126	0	385	0	0
T127	537707	0	0	0
T128	775	0	0	0
T129	221575	0	0	0
T130	92005	0	0	0
T131	195175	0	0	0
T132	39374	0	0	0
T133	740846	0	0	0
T134	306995	0	0	0