Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15839241

1

T3

99

T4

919

T5

86

full_word

136784783

1

T3

935

T4

8600

T5

883

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	152623714	1			T3	1034		T4	9519		T5	969
auto[TlIntgErrCmd]	99	1			T72	1		T73	5		T74	6
auto[TlIntgErrData]	112	1			T72	3		T73	8		T74	9
auto[TlIntgErrBoth]	99	1			T72	6		T73	7		T74	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72978485

1

T3

489

T4

4784

T5

486

auto[1]

79645539

1

T3

545

T4

4735

T5

483

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7725609	1			T3	50		T4	449		T5	53
auto[TlIntgErrNone]	partial	auto[1]	8113347	1			T3	49		T4	470		T5	33
auto[TlIntgErrNone]	full_word	auto[0]	65252729	1			T3	439		T4	4335		T5	433
auto[TlIntgErrNone]	full_word	auto[1]	71532029	1			T3	496		T4	4265		T5	450
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T73	1		T74	2		T143	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T72	1		T73	3		T74	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T139	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T73	1		T142	1		T146	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T72	1		T73	6		T74	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T72	2		T73	1		T74	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T143	1		T147	1		T145	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T73	1		T143	2		T148	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T72	3		T73	5		T74	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T72	2		T73	2		T143	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T74	1		T145	1		T149	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T72	1		T74	1		T143	1