Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	644441	1			T11	23		T34	724		T35	241
auto[1]	11374359	1			T7	1759		T8	1350		T11	106
auto[2]	483408	1			T11	8		T34	680		T35	139
auto[3]	11102278	1			T7	1757		T8	1449		T11	122

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15545932	1			T7	2324		T8	1891		T11	192
auto[1]	2162729	1			T7	540		T8	402		T11	21
auto[2]	2203416	1			T7	544		T8	419		T11	43
auto[3]	3692409	1			T7	108		T8	87		T11	3

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10249145

1

T7

3516

T8

2799

T11

259

auto[1]

13355341

1

T29

1

T28

1

T69

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	243407	1			T11	19		T34	18		T35	194
auto[0]	auto[0]	auto[1]	25935	1			T11	1		T34	120		T35	24
auto[0]	auto[0]	auto[2]	26078	1			T11	3		T34	102		T35	21
auto[0]	auto[0]	auto[3]	47192	1			T34	484		T35	2		T88	3
auto[0]	auto[1]	auto[0]	3825601	1			T7	1142		T8	899		T11	84
auto[0]	auto[1]	auto[1]	391309	1			T7	277		T8	195		T11	15
auto[0]	auto[1]	auto[2]	407389	1			T7	282		T8	212		T11	6
auto[0]	auto[1]	auto[3]	309218	1			T7	58		T8	44		T11	1
auto[0]	auto[2]	auto[0]	169138	1			T34	23		T35	110		T128	42
auto[0]	auto[2]	auto[1]	19944	1			T34	106		T35	14		T88	1
auto[0]	auto[2]	auto[2]	22319	1			T11	8		T34	96		T35	15
auto[0]	auto[2]	auto[3]	34858	1			T34	455		T88	3		T128	794
auto[0]	auto[3]	auto[0]	3658572	1			T7	1182		T8	992		T11	89
auto[0]	auto[3]	auto[1]	388577	1			T7	263		T8	207		T11	5
auto[0]	auto[3]	auto[2]	398408	1			T7	262		T8	207		T11	26
auto[0]	auto[3]	auto[3]	281200	1			T7	50		T8	43		T11	2
auto[1]	auto[0]	auto[0]	10258	1			T118	265		T165	92		T166	838
auto[1]	auto[0]	auto[1]	44888	1			T118	1146		T165	539		T166	3417
auto[1]	auto[0]	auto[2]	44895	1			T118	1109		T165	507		T166	3414
auto[1]	auto[0]	auto[3]	201788	1			T97	1		T118	5185		T165	2415
auto[1]	auto[1]	auto[0]	3819238	1			T70	46055		T71	2611		T117	2646
auto[1]	auto[1]	auto[1]	645925	1			T70	4119		T71	10786		T117	10756
auto[1]	auto[1]	auto[2]	631549	1			T70	4609		T71	12103		T117	11847
auto[1]	auto[1]	auto[3]	1344130	1			T70	408		T167	1		T71	48346
auto[1]	auto[2]	auto[0]	6611	1			T118	165		T166	769		T168	457
auto[1]	auto[2]	auto[1]	29233	1			T118	707		T166	3114		T168	2089
auto[1]	auto[2]	auto[2]	36259	1			T118	1151		T165	440		T166	2361
auto[1]	auto[2]	auto[3]	165046	1			T69	1		T118	4973		T165	2031
auto[1]	auto[3]	auto[0]	3813107	1			T29	1		T28	1		T70	46423
auto[1]	auto[3]	auto[1]	616918	1			T70	4607		T71	11769		T117	11669
auto[1]	auto[3]	auto[2]	636519	1			T70	4159		T96	1		T71	10624
auto[1]	auto[3]	auto[3]	1308977	1			T70	411		T71	48394		T117	48406